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Kyoko Izuha
Kyoko Izuha, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090265680 | Method and system for correcting a mask pattern design - A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics. | 10-22-2009 |
| 20110041104 | Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device - A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected. | 02-17-2011 |
Kyoko Izuha, Atsugi-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090291512 | SEMICONDUCTOR DEVICE PATTERN VERIFICATION METHOD, SEMICONDUCTOR DEVICE PATTERN VERIFICATION PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Information on a transfer pattern created from a design pattern corresponding to a pattern to be formed on a substrate is acquired as pattern transfer information. The design pattern is compared with the transfer pattern and, on the basis of the feature quantity obtained from the comparison, the pattern transfer information and the design pattern are classified. A threshold value is set for the feature quantity and, on the basis of the threshold value, the pattern transfer information and the design pattern are further classified. Then, verification is conducted to see if the transfer pattern satisfies the threshold value. | 11-26-2009 |