Patent application number | Description | Published |
20080299770 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 12-04-2008 |
20090032964 | System and method for providing semiconductor device features using a protective layer - Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises disposing a protective layer over the first side of the substrate, removing a portion of the protective layer over at least a portion of the opening to provide access to the hole, and filling at least a portion of the hole with a fill material. | 02-05-2009 |
20090159208 | METHOD OF FORMING TEMPORARY CARRIER STRUCTURE AND ASSOCIATED RELEASE TECHNIQUES - A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to a depth that is less than a thickness of the carrier structure, forming a dissolvable material in the recesses and above a first surface of the carrier structure, securing a thin substrate above the first surface of the carrier structure using the dissolvable material to secure the thin substrate in place, performing at least one process operation on a second surface of the carrier structure to expose the dissolvable material in the recesses and contacting the exposed dissolvable material with a release agent so as to dissolve at least a portion of the dissolvable material. | 06-25-2009 |
20090215263 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 08-27-2009 |
20090315154 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 12-24-2009 |
20100171217 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 07-08-2010 |
20110204526 | Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices - The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated. | 08-25-2011 |
20110233777 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 09-29-2011 |
20110241205 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 10-06-2011 |
20110284152 | METHOD OF FORMING TEMPORARY CARRIER STRUCTURE AND ASSOCIATED RELEASE TECHNIQUES - A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to a depth that is less than a thickness of the carrier structure, forming a dissolvable material in the recesses and above a first surface of the carrier structure, securing a thin substrate above the first surface of the carrier structure using the dissolvable material to secure the thin substrate in place, performing at least one process operation on a second surface of the carrier structure to expose the dissolvable material in the recesses and contacting the exposed dissolvable material with a release agent so as to dissolve at least a portion of the dissolvable material. | 11-24-2011 |