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Kwong, CA
Bill Kwong, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080218959 | Combo internal and external storage system - A combo internal and external storage system which comprising: an enclosure portion, having a plurality of openings on it's real wall and a hollow space for containing the storage device which further comprises a first power interface and a first data interface; and a first PCB, being disposed in the hollow space and further comprising a first connector, a second power interface, a second data interface, a second connector and a power connector; wherein the first connector is used to connect to the first power interface and first data interface of the storage device, the second data interface and second data interface are used to connect to a power interface and data interface of the cradle portion, and the second connector and power connector are used to connect to the computer or equipment by the cable. | 09-11-2008 |
| 20100205454 | CIPHER DATA BOX - A cipher data box comprises: a housing; a printed circuit board; a first connector; a second connector; a controller, having a unique first identification code; a key seat; and a key, having a unique second identification code; therefore, when the key is inserted into the key seat and the first identification code is same as the second identification code, the storage device can be normally accessed, and the data therein will be encrypted/decrypted. Furthermore, for further enhancing the security function of the storage device, a plurality of cipher data boxes of the present invention can be cascade each other. | 08-12-2010 |
David Kwong, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090199149 | METHODS AND APPARATUS FOR LAYOUT OF MULTI-LAYER CIRCUIT SUBSTRATES - Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are proviuded on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second radius R | 08-06-2009 |
David Kwok Kuen Kwong, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080238396 | Feedback controller having multiple feedback paths - A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value. | 10-02-2008 |
| 20090045867 | FUSE CELL AND METHOD FOR PROGRAMMING THE SAME - The fuse cell architecture | 02-19-2009 |
| 20090091399 | LOW VOLTAGE SYNCHRONOUS OSCILLATOR FOR DC-DC CONVERTER - Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions. | 04-09-2009 |
David Kwok Kuen Kwong, Davis, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090140808 | GAIN CONTROL CIRCUIT - A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs. | 06-04-2009 |
| 20090146749 | Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch - An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage. | 06-11-2009 |
Gabriel A. Kwong, Alhambra, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090017455 | Methods and systems for detecting and/or sorting targets - Provided herein are methods and systems for detecting and/or sorting targets in a sample based on the combined use of polynucleotide-encoded-protein and substrate polynucleotides. The polynucleotide-encoded protein is comprised of a protein that specifically binds to a predetermined target and of an encoding polynucleotide that specifically binds to a substrate polynucleotide, wherein the substrate polynucleotide is attached to a substrate. | 01-15-2009 |
| 20110039717 | METHODS AND SYSTEMS FOR DETECTING AND/OR SORTING TARGETS - Provided herein are methods and systems for detecting and/or sorting targets in a sample based on the combined use of polynucleotide-encoded protein and substrate polynucleotides. The polynucleotide-encoded protein is comprised of a protein that specifically binds to a predetermined target and of an encoding polynucleotide that specifically binds to a substrate polynucleotide, wherein the substrate polynucleotide is attached to a substrate. | 02-17-2011 |
| 20110166034 | CAPTURE AGENTS AND RELATED METHODS AND SYSTEMS FOR DETECTING AND/OR SORTING TARGETS - Polynucleotide-encoded capture agents for target detection and in particular modular polynucleotide-capture agents comprising a target binding component, a scaffold component and an encoding component formed by standardized molecular units that can be coupled and decoupled in a controlled fashion, and related compositions methods and systems. | 07-07-2011 |
Garry Kwong, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090277006 | METHOD FOR FORMING AN ELECTRICAL CONNECTION - Embodiments of the present invention provide a method of forming an electrical connection on a device. In one embodiment, the electrical connection is attached to the device via an adhesive having electrically conductive particles disposed therein. In one embodiment, the adhesive is cured while applying pressure such that the conductive particles align, have a reduced particle-to-particle spacing, or come into contact with each other to provide a more directly conductive (less resistive) path between the electrical connection and the device. In one embodiment of the present invention, a method for forming an electrical lead on a partially formed solar cell during formation of the solar cell device is provided. The method comprises placing a side-buss wire onto a pattern of electrically conductive adhesive disposed on a back contact layer of a solar cell device substrate, laminating the side-buss wire and electrically conductive adhesive between the solar cell device substrate and a back glass substrate to form a composite solar cell structure, and curing the electrically conductive adhesive while applying pressure and heat to the composite solar cell structure | 11-12-2009 |
| 20100071752 | Solar Cell Module Having Buss Adhered With Conductive Adhesive - Solar cell modules and methods for making solar cell modules are disclosed. In one or more embodiments of the invention, a buss is adhered to the solar cell modules using a plurality of conductive adhesive drops. | 03-25-2010 |
Herman Kwong, Danville, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110209094 | SYSTEMS AND METHODS FOR IMPLEMENTING CUSTOMIZED DROP-DOWN MENUS - Systems and methods for implementing customized drop-down menus in user interface displays. Drop-down menus include one or more selection options and a table having multiple fields. Drop-down menu items are particularly useful for assisting a user with assigning information synchronized into a target database from one database system, such as an Outlook file, to objects in the target database system, such as a multi-tenant database system as well as providing suggestions to the user from search results when they may want to choose one of those results or perform a different action altogether. | 08-25-2011 |
| 20110238622 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ASSOCIATING A RECORD WITH AN ACCOUNT FROM AN ON-DEMAND DATABASE SYSTEM - In accordance with embodiments, there are provided mechanisms and methods for associating a record with an account from an on-demand database system. These mechanisms and methods for associating a record with an account from an on-demand database system can enable improved synchronization between an on-demand database system and a software element separate from the on-demand database system, etc. | 09-29-2011 |
| 20120102402 | Framework for Custom Actions on an Information Feed - Systems and methods for providing a custom action for an information post are described. In one embodiment, data for generating a user interface component for display at a client machine may be transmitted from a server to the client machine. The user interface component displaying one or more information posts may be capable of being generated in accordance with first computing programming language instructions provided by a first entity. Each information post may include information relating to a record stored on a storage medium accessible to the server. Selected ones of the information posts may have associated therewith a custom action activation mechanism for activating a custom action relating to the associated information post. The custom action activation mechanism may be capable of being generated in accordance with second computer programming language instructions provided by a second entity. | 04-26-2012 |
Janifer W. Kwong, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110197493 | Multi-Functional Fishing Lure Assembly - A multi-functional fishing lure assembly to generate visual simulation and scent, the multi-functional fishing lure assembly consists essentially of a soft, flexible and elongated body portion which has two ends, one end detachably coupled with a fishing hook, the opposite end attached integrally to an elongated tail portion, a chamber that has an opening disposed in the elongated body portion and covered by a lid portion which has slits and apertures, a volume of active ingredients that contains scent material, color material, bubbles generating material and combination thereof, which can be reloaded and reused. | 08-18-2011 |
Justin Y Kwong, Sandiego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090041306 | Living Body Variable Measuring System with Wireless Internet Access and Biometric Authentication - A physiological data measurement and analysis system comprises: a central processing centre for receiving physiological data for at least one subject, analysing the data and generating physiological information related to improving the subject's physiological condition based on the analysed data; at least one satellite station for measuring and transmitting selected physiological data of at least one subject to the central processing centre and receiving the generated physiological information from the central processing centre; and a communications network for coupling the central processing centre to each satellite station. | 02-12-2009 |
Karric Kwong, Vallejo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100017102 | METHOD AND APPARATUS GENERATING AND/OR USING ESTIMATES OF ARTERIAL VEHICULAR MOVEMENT - A roadway information system is disclosed with components generating and using vehicle signatures for vehicles passing near sensor pods located on or near lanes. These components in turn are part of and/or communicate with means and/or processors for generating an/or using Vehicle Movement Estimates based upon the vehicle signatures. The VME are used to create traffic feedback that may be presented to programmable field devices that may present at least some of the traffic feedback to drivers of the vehicles, thereby optimizing the fuel usage and travel time of the roadway. | 01-21-2010 |
| 20100017103 | METHOD AND APPARATUS GENERATING ESTIMATES VEHICULAR MOVEMENT INVOLVING MULTIPLE INPUT-OUTPUT ROADWAY NODES - A roadway information system is disclosed with components generating and using vehicle signatures for vehicles passing near sensor pods located on or near lanes in a multiple input-output roadway node. Means and/or processors for matching incoming and outgoing vehicle signatures are disclosed creating an in-out vehicle match table used to generate a vehicle movement estimate or its components including a travel time and/or vehicle count that may be created and/or used in response to a match tally exceeding a threshold or the stimulation of a timing signal. | 01-21-2010 |
| 20100017104 | METHOD AND APPARATUS MATCHING INCOMING TO OUTGOING VEHICLE SIGNATURES TO ESTIMATE ARTERIAL VEHICULAR MOVEMENT - A roadway information system is disclosed with components generating and using vehicle signatures for vehicles passing near sensor pods located on or near lanes. Means and/or processors for matching incoming and outgoing vehicle signatures are disclosed creating an in-out vehicle match table used to generate a vehicle movement estimate or its components including a travel time and/or vehicle count. | 01-21-2010 |
Kwok Kuen Kwong, Davis, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100073070 | Low Voltage High-Output-Driving CMOS Voltage Reference With Temperature Compensation - A bandgap reference voltage generator has a first stage that generates a first current that is complementary-to-absolute-temperature (Ictat) and a second stage that generates a current that is proportional-to-absolute-temperature (Iptat). The Ictat and Iptat currents are both forced through a summing resistor to generate a voltage that is relatively independent of temperature, since the Ictat and Iptat currents cancel out each other's temperature dependencies. A PMOS output transistor drives current to an output load to maintain the load at the reference voltage. An op amp drives the gate of the PMOS output transistor and has inputs connected to emitters of PNP transistors in the second stage. A series of resistors generate the reference voltage between the PMOS output transistor and ground and drives bases of the PNP transistors and includes the summing resistor. Parasitic PNP transistors in an all-CMOS process are used. The generator operates with a 1-volt power supply. | 03-25-2010 |
| 20100148727 | Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock - A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor. | 06-17-2010 |
| 20100164770 | MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING - An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period. | 07-01-2010 |
| 20100315748 | ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs - An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor. | 12-16-2010 |
| 20110216559 | Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter - A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control. | 09-08-2011 |
| 20110267008 | Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock - A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor. | 11-03-2011 |
| 20120126736 | Bootstrapped High-Side Driver Control Without Static DC Current for Driving a Motor Bridge Circuit - A motor driver circuit for driving the gate node of a high-side driver transistor to a boosted voltage from a charge pump draws little or no static current from the charge pump. The gate node is pulled to the boosted voltage by a p-channel pullup-control transistor that is driven by p-channel transistors that are pumped by capacitors that cut off current flow to ground from the charge pump. An n-channel output-shorting transistor shorts the gate node to the output when the high-side driver is turned off. A coupling capacitor initializes the shorting transistor for each output transition. A p-channel output-sensing transistor generates a feedback to a second stage that drives the coupling capacitor. P-channel diode transistors and an n-channel equalizing transistor control the voltage on the coupling capacitor. | 05-24-2012 |
| 20120126901 | PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE - A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC. | 05-24-2012 |
Kwok Kuen (david) Kwong, Davis, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090134923 | ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL) - A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL. | 05-28-2009 |
| 20100164625 | Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps - An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers. | 07-01-2010 |
| 20100164761 | DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC - A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes. | 07-01-2010 |
| 20110163799 | Bi-directional Trimming Methods and Circuits for a Precise Band-Gap Reference - A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process. | 07-07-2011 |
| 20110221938 | Optical Black-Level Cancellation for Optical Sensors Using Open-Loop Sample Calibration Amplifier - A Optical Black Pixel (OBP) cancellation circuit corrects offsets in sensors in a CCD/CMOS image sensor when reading dark pixels such at the periphery. A pixel voltage is switched to a sampling capacitor during two phases of the same pixel pulse. Sampling capacitors and feedback capacitors connect to differential inputs of an amplifier. An accumulating capacitor accumulates voltage differences and generates a common-mode voltage that is fed back to another sampling capacitor that stores an amplifier offset. The sampling capacitor and accumulating capacitor and their associated switches form a discrete-time first-order low-pass filter that filters the pixel voltage during the first phase. In the second phase the amplifier acts as a unity-gain amplifier to output an average of the pixel voltage differences generated during an OBP time when blackened or covered pixels are read from the image sensor. | 09-15-2011 |
Lancelot Kwong, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090303819 | WRITE AND READ ASSIST CIRCUIT FOR SRAM WITH POWER RECYCLING - A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging. | 12-10-2009 |
Lancelot Y. Kwong, Freemont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120126852 | HIGH-SPEED STATIC XOR CIRCUIT - A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal. | 05-24-2012 |
Lancelot Y. Kwong, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090213641 | MEMORY WITH ACTIVE MODE BACK-BIAS VOLTAGE CONTROL AND METHOD OF OPERATING SAME - Data storage cells of a static random access memory array are selectively provided with back-bias voltages to reduce current leakage during an active mode of operation. Circuitry electrically connected with the array receives control signals and provides the back-bias voltages to certain idle data storage cells of the array based on the control signals. | 08-27-2009 |
Leslie W. Kwong, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110197493 | Multi-Functional Fishing Lure Assembly - A multi-functional fishing lure assembly to generate visual simulation and scent, the multi-functional fishing lure assembly consists essentially of a soft, flexible and elongated body portion which has two ends, one end detachably coupled with a fishing hook, the opposite end attached integrally to an elongated tail portion, a chamber that has an opening disposed in the elongated body portion and covered by a lid portion which has slits and apertures, a volume of active ingredients that contains scent material, color material, bubbles generating material and combination thereof, which can be reloaded and reused. | 08-18-2011 |
Michael Yiupun Kwong, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100332473 | CORRELATING QUERIES ISSUED BY APPLICATIONS WITH THEIR SOURCE LINES AND ANALYZING APPLICATIONS FOR PROBLEM DETERMINATION AND WHERE USED ANALYSIS - Provided are techniques for invoking with a processor executing on a computer a source code parser to obtain source information that includes a first location of an Application Programming Interface (API) call and parameters of the API call in source code of a client application, where the parameters the API call do not include query text for a query that is to be used to access a database; examining a stack trace to determine a second location of the API call in the stack trace; and deriving the query of the API call and a third location of the query in the source code by identifying the query in the stack trace at the location of the API call in the stack trace. | 12-30-2010 |
Norman Kwong, San Marino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090067465 | MULTIPLE CAVITY ETCHED-FACET DFB LASERS - A semiconductor chip has at least two DFB etched facet laser cavities with one set of facets with AR coatings and a second set of etched facets with HR coatings that have a different relative position with respect to the gratings. This creates a difference in the phase between each of the etched facets and the gratings which changes the operational characteristics of the two laser cavities such that at least one of the lasers provides acceptable performance. As a result, the two cavity arrangement greatly improves the yield of the fabricated chips. | 03-12-2009 |
Norman S. Kwong, San Marino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080219316 | Laser and Monitoring Photodetector with Polymer Light Guide - A surface emitting laser ( | 09-11-2008 |
Raymond Wai-Kit Kwong, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100333191 | SYSTEM AND METHOD FOR PROTECTING CPU AGAINST REMOTE ACCESS ATTACKS - A system and method that provides for protection of a CPU of a router, by establishing a management port on a router. Hosts which are connected to a non-management ports of the router are denied access to management functions of a CPU of the router. The system and method can utilize an application specific integrated circuit, in conjunction with a CAM-ACL, which analyzes data packets received on the ports of router, and the ASIC operates to drop data packets which are directed to the CPU of the router. This system and method operates to filter data packets which may be generated in attempts to hack in to control functions of a network device, and the operation does not require that the CPU analyze all received data packets in connection with determining access to the control functions of the router. | 12-30-2010 |
Thomas Kwong, Temple City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110022623 | SYSTEM AND METHOD FOR INFLUENCING A POSITION ON A SEARCH RESULT LIST GENERATED BY A COMPUTER NETWORK SEARCH ENGINE - A system and method for enabling information providers using a computer network such as the Internet to influence a position for a search listing within a search result list generated by an Internet search engine. The system and method of the present invention provides a database having accounts for the network information providers. Each account contains at least one search listing having at least three components: a description, a search term comprising one or more keywords, and a bid amount. The network information provider may add, delete, or modify a search listing after logging into his or her account via an authentication process. The network information provider influences the position for a search listing through a continuous online competitive bidding process. The bidding process occurs when the network information provider enters a new bid amount, which is preferably a money amount, for a search listing. The system then compares this bid amount with all other bid amounts for the same search term, and generates a rank value for all search listings having that search term. The rank value generated by the bidding process determines where the network information providers listing will appear on the search results list page that is generated in response to a query of the search term by a searcher located at a client computer on the computer network. A higher bid by a network information provider will result in a higher rank value and a more advantageous placement. | 01-27-2011 |