| Patent application number | Description | Published |
|---|
| 20090002387 | Method and apparatus for rendering three dimensional graphics data - Provided is a method and apparatus for rendering 3D graphics data. By calculating the size of a primitive, which is a basic constituent unit of objects indicated by the graphics data, on a screen, selecting one of a plurality of resolutions supported by a video stream according to the calculated size, generating a video frame image having the selected resolution from the video stream, and rendering the graphics data using the generated video frame image, the amount of memory space used and power consumed are reduced. In addition, since when rendering is performed using a video frame image decoded at a low resolution, a processing speed increases, and since rendering can be performed using video frame images decoded at various resolutions, image quality increases. | 01-01-2009 |
| 20090089551 | Apparatus and method of avoiding bank conflict in single-port multi-bank memory system - Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict. | 04-02-2009 |
| 20090167777 | Method and apparatus for rendering - A rendering method and apparatus are provided. The rendering method includes: performing texture mapping of a transparency value of a fragment; testing whether or not the fragment can be expressed as a pixel after the performing of the texture mapping; and selectively performing texture mapping of the color value of the fragment according to the test result. | 07-02-2009 |
| 20090184959 | Method and apparatus for rendering - A rendering apparatus and method are provided. The rendering method includes: reading a block, corresponding to a fragment, from among compressed blocks stored in a depth buffer, by considering frequency information corresponding to the fragment and prepared in advance; and performing a depth test for the fragment by considering the restored block. | 07-23-2009 |
| 20100103164 | Apparatus and method of processing three dimensional graphic data using texture factor - A method and apparatus of processing three-dimensional (3D) graphic data using a texture factor. The method of processing 3D graphic data includes configuring a polygon including a plurality of vertexes, calculating a texture factor of an object texture corresponding to the polygon, the texture factor being associated with a degree by which the object texture is identified on an actual screen, and determining a texture filtering mode with respect to the object texture based on the calculated texture factor. | 04-29-2010 |
| 20100110091 | Apparatus and method of reading texture data for texture mapping - An apparatus and method of reading texture data for texture mapping. Each of a plurality of blocks included in a cache memory may have any one of an even numbered index or odd numbered index. In this instance, the cache memory may be embodied with an odd numbered index cache memory including odd numbered index blocks and an even numbered index cache memory including even numbered index blocks. Also, address indexes of requested texture data may be analyzed to appropriately access to at least one of the odd numbered index cache memory and even numbered index cache memory, thereby improving an accessing speed. | 05-06-2010 |
| 20100115141 | Processor and method for controlling memory - A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate. | 05-06-2010 |
| 20110090224 | Tile-based rendering apparatus and method - A tile based rendering apparatus and method is provided. The rendering method may be used to graphically represent a three dimensional (3D) model on a two dimensional (2D) display screen. Also, the rendering method may perform pre-binning with respect to objects included in a frame, and thus all geometry processing results may not be stored in an external memory and use of the external memory may be reduced. | 04-21-2011 |
| 20110099555 | Reconfigurable processor and method - Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread. | 04-28-2011 |
| 20110164692 | Apparatus and method for converting protocol interface - An apparatus and method for converting a protocol interface are provided. A protocol converter may analyze a protocol of protocol data, and may sequentially output a plurality of sub-data of the input protocol data according to types of the plurality of sub-data and a plurality of phase information representing the types of the plurality of sub-data. A phase channel line may transmit phase information received from the protocol converter among the plurality of phase information. A data channel line may simultaneously transmit the received phase information and a sub-data corresponding to the received phase information. | 07-07-2011 |
