Patent application number | Description | Published |
20090315137 | SEMICONDUCTOR DEVICES, CMOS IMAGE SENSORS, AND METHODS OF MANUFACTURING SAME - A semiconductor device includes: a trench device isolating region formed in a substrate to define a photodiode active region; a channel stop impurity region formed in the substrate contacting the device isolating region, wherein the channel stop impurity region surrounds a bottom and a sidewall of the device isolating region; and a photodiode formed within the photodiode active region. | 12-24-2009 |
20100176474 | BACK-LIT IMAGE SENSOR AND METHOD OF MANUFACTURE - A backside-illuminated image sensor includes photoelectric converters disposed in a front-side of a substrate and arranged to define pixels, back-side interlayer dielectric patterns disposed on the back-side of the substrate over the photoelectric converters, color filters arranged over the back-side interlayer dielectric patterns, and micro-lenses arranged over the color filters, wherein adjacent back-side interlayer dielectric patterns are separated by an intervening gap region having a refractive index less than that of the back-side interlayer dielectric patterns. | 07-15-2010 |
20110291219 | BACKSIDE ILLUMINATION IMAGE SENSOR, METHOD OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE BACKSIDE ILLUMINATION IMAGE SENSOR - A backside illumination image sensor, a method of fabricating the same, and an electronic system including the backside illumination image sensor, the backside illumination image sensor including a semiconductor substrate, the semiconductor substrate having an upper surface and a lower surface; photodiodes in the semiconductor substrate; and metal interconnections below the semiconductor substrate, wherein each of the photodiodes includes a N-type region, a lower P-type region below the N-type region, and an upper P-type region on the N-type region. | 12-01-2011 |
20130307110 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including a front side and a back side opposite the front side, first P-type regions located adjacent to the back side and spaced apart from each other in the substrate, N-type regions located under the first P-type regions and spaced apart from each other in the substrate, and second P-type regions located adjacent to the back side and located between the first P-type regions. | 11-21-2013 |
20150076649 | STACK TYPE IMAGE SENSORS AND METHODS OF MANUFACTURING THE SAME - An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer. | 03-19-2015 |
Patent application number | Description | Published |
20110042797 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package. | 02-24-2011 |
20120074595 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate on which a first semiconductor chip is mounted, a second substrate spaced apart from the first substrate and on which a second semiconductor chip is mounted, first pads disposed on the first substrate, second pads disposed on the second substrate to be opposite to the first pads, and connection patterns electrically connecting the opposite first and second pads to each other, respectively. The first pads are disposed asymmetrically with respect to the central axis of the first substrate. | 03-29-2012 |
20120299197 | SEMICONDUCTOR PACKAGES - Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter. | 11-29-2012 |
20130091348 | SURFACE TEMPERATURE MANAGEMENT METHOD OF MOBILE DEVICE AND MEMORY THERMAL MANAGEMENT METHOD OF MULTICHIP PACKAGE - A surface temperature management method of mobile device is provided. The method includes sensing a temperature of an application processor in an operation mode of the mobile device; and controlling the application processor using the sensed temperature and a surface temperature management table to manage a surface temperature of a target part of the mobile device. The surface temperature management table includes information related to the temperature of the application processor corresponding to the surface temperature of the target part in the operation mode. | 04-11-2013 |
20130203219 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package. | 08-08-2013 |
20140374900 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes memory I/O bumps and power/ground voltage bumps which are disposed at different positions from each other. In the semiconductor package, memory chips are disposed side by side, and a passivation layer is interposed between a conductive pad and a bump. | 12-25-2014 |
20150014862 | SEMICONDUCTOR PACKAGES INCLUDING A METAL LAYER BETWEEN FIRST AND SECOND SEMICONDUCTOR CHIPS - Semiconductor packages are provided. A semiconductor package may include a wiring board and a first semiconductor chip on the wiring board. Moreover, the semiconductor package may include a metal layer on the first semiconductor chip and a second semiconductor chip on the metal layer. The metal layer may be between the first and second semiconductor chips. | 01-15-2015 |
20150048521 | SEMICONDUCTOR PACKAGE - According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package. | 02-19-2015 |
Patent application number | Description | Published |
20080246162 | Stack package, a method of manufacturing the stack package, and a digital device having the stack package - A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips. | 10-09-2008 |
20100044852 | VERTICAL STACK TYPE MULTI-CHIP PACKAGE HAVING IMPROVED GROUNDING PERFORMANCE AND LOWER SEMICONDUCTOR CHIP RELIABILITY - A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate. | 02-25-2010 |
20110084380 | SEMICONDUCTOR PACKAGES HAVING PASSIVE ELEMENTS MOUNTED THEREONTO - A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface. | 04-14-2011 |
20110116247 | SEMICONDUCTOR PACKAGE HAVING MULTI PITCH BALL LAND - A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch. | 05-19-2011 |
20110149493 | STACKED SEMICONDUCTOR PACKAGES, METHODS OF FABRICATING THE SAME, AND/OR SYSTEMS EMPLOYING THE SAME - An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. | 06-23-2011 |
20110233771 | SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package. | 09-29-2011 |
20120091597 | STACKED SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE INCLUDING THE STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side. | 04-19-2012 |
20120280404 | STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR - A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate. | 11-08-2012 |
20130009308 | SEMICONDUCTOR STACK PACKAGE APPARATUS - A semiconductor stack package apparatus includes an upper semiconductor package and a lower semiconductor package. The upper semiconductor chip includes a chip pad, an upper substrate including a substrate pad formed on a top surface of the upper substrate and an upper ball land formed on a bottom surface of the upper substrate and attached to an intermediate solder ball, and a wire connecting the chip pad and the substrate pad. The lower semiconductor package includes a lower semiconductor chip including a bump, and a lower substrate including a bump land formed on a top surface of the lower substrate in an area corresponding to the bump, an intermediate ball land formed on the top surface of the lower substrate in an area corresponding to the intermediate solder ball, and a lower ball land formed on a bottom surface of the lower substrate and attached to a lower solder ball. | 01-10-2013 |
20130043584 | SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit. | 02-21-2013 |
20130099373 | SEMICONDUCTOR PACKAGES INCLUDING A PLURALITY OF UPPER SEMICONDUCTOR DEVICES ON A LOWER SEMICONDUCTOR DEVICE - Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other. | 04-25-2013 |
20130154103 | SEMICONDUCTOR PACKAGE HAVING MULTI PITCH BALL LAND - A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch. | 06-20-2013 |
20130208426 | SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER AND METHOD OF FORMING THE SAME - A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern. | 08-15-2013 |
20130256916 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES - A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package. | 10-03-2013 |
20130292828 | STACKED SEMICONDUCTOR PACKAGES - An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. | 11-07-2013 |
20130334708 | STACKED SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTIONS OF VARYING HEIGHTS BETWEEN SUBSTRATES, AND SEMICONDUCTOR DEVICE INCLUDING THE STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side. | 12-19-2013 |
20140077382 | SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package. | 03-20-2014 |
20140159237 | SEMICONDUCTOR PACKAGE AND METHOD FOR ROUTING THE PACKAGE - A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate. | 06-12-2014 |
20140167260 | SEMICONDUCTOR PACKAGES INCLUDING A PLURALITY OF UPPER SEMICONDUCTOR DEVICES ON A LOWER SEMICONDUCTOR DEVICE - Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other. | 06-19-2014 |
20140175679 | SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit. | 06-26-2014 |
20140193951 | STACKED SEMICONDUCTOR PACKAGE INCLUDING CONNECTIONS ELECTRICALLY CONNECTING FIRST AND SECOND SEMICONDUCTOR PACKAGES - A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side. | 07-10-2014 |
20140324245 | APPLICATION PROCESSOR AND DYNAMIC THERMAL MANAGEMENT METHOD THEREOF - Provided is a dynamic thermal management method performed by an application processor which stores a first dynamic voltage and frequency scaling (DVFS) table and a second DVFS table, the method including comparing a surface temperature of a mobile apparatus with a critical surface temperature, controlling performance of the application processor according to the first DVFS table when the surface temperature is less than the critical surface temperature, and controlling performance of the application processor according to the second DVFS table when the surface temperature is not less than the critical surface temperature. | 10-30-2014 |
20140335657 | STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR - A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate. | 11-13-2014 |
Patent application number | Description | Published |
20100266891 | SECONDARY BATTERY PACK BASED ON MECHANICAL CONNECTION MANNER - Disclosed herein is a battery pack constructed in a structure in which a plurality of secondary battery cells are electrically connected to one another via a connection member while the secondary battery cells are mounted in a receiving part of a pack case having no partition, wherein the connection member is located between the battery cells arranged in the longitudinal direction or in both the longitudinal direction and the lateral direction, the connection member is connected, in a mechanical coupling manner, to a lower electrode terminal of the front battery cell in the longitudinal direction and/or to an upper electrode terminal of the rear battery cell in the longitudinal direction, and the connection member is elastically pressed while the connection member is located between the battery cells. | 10-21-2010 |
20110104958 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner, for minimizing the change of resistance at the contact region against an external force and restraining a possibility that the electrode terminal of the lower battery cell is depressed, and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 05-05-2011 |
20130065457 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 03-14-2013 |
20130202948 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 08-08-2013 |
20130280969 | SECONDARY BATTERY PACK BASED ON MECHANICAL CONNECTION MANNER - Disclosed herein is a battery pack constructed in a structure in which a plurality of secondary battery cells are electrically connected to one another via a connection member while the secondary battery cells are mounted in a receiving part of a pack case having no partition, wherein the connection member is located between the battery cells arranged in the longitudinal direction or in both the longitudinal direction and the lateral direction, the connection member is connected, in a mechanical coupling manner, to a lower electrode terminal of the front battery cell in the longitudinal direction and/or to an upper electrode terminal of the rear battery cell in the longitudinal direction, and the connection member is elastically pressed while the connection member is located between the battery cells. | 10-24-2013 |
20140017554 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 01-16-2014 |
20140127545 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 05-08-2014 |
20140154550 | ELECTRICAL CONNECTING MEMBER FOR SECONDARY BATTERY - Disclosed herein is a connection member for secondary batteries to achieve the electrical connection in a battery pack including two or more cylindrical secondary batteries in a physical contact manner, the connection member including an outer circumferential contact part contacting an electrode terminal of a lower battery cell along the outer circumferential region of the electrode terminal of the lower battery cell, such that the outer circumferential contact part can be electrically connected to the electrode terminal of the lower battery cell in a surface contact manner and a central contact part contacting an electrode terminal of an upper battery cell or the central region of a sidewall of the battery pack for providing an elastic contact force to the entire connection member mounted between the electrode terminals of the respective battery cells or between the electrode terminals of the battery cells and the sidewall of the battery pack. | 06-05-2014 |
Patent application number | Description | Published |
20100301591 | ROOF AIRBAG APPARATUS WITH AIRBAG DOOR HAVING LIMITED OPENING ANGLE - A roof airbag apparatus, may include an inflator, a housing mounted to an opening frame provided in a vehicle roof, the opening frame defining an opening therein to receive the housing, an airbag cushion contained in the housing, the airbag cushion being deployed downwards by gas supplied from the inflator to protect a passenger, an airbag door coupled to the housing by a hinge to support the airbag cushion, and angle limiting means for limiting a rotating angle to a predetermined angle when the airbag door is rotated to open. | 12-02-2010 |
20110115200 | AIRBAG MOUNTING ASSEMBLY FOR VEHICLES - An airbag mounting assembly for vehicles to mount a passenger airbag housing to a cowl cross bar may include a mounting bracket, a first end thereof being mounted to the passenger airbag housing and a fastening unit mounting a second end of the mounting bracket to the cowl cross bar. | 05-19-2011 |
20120032425 | Pre-Crash Side Air Bag Device - A pre-crash side airbag device includes a side collision detection sensor, a pre-crash sensor, a main airbag, an auxiliary airbag, and a control unit. The side collision detection sensor detects a collision occurring at the side of a vehicle. The pre-crash sensor detects physical quantities related to the speed of an approaching object. The main airbag is deployed when a control signal is input. The auxiliary airbag is coupled to one side of the main airbag. The control unit controls the deployment of the main airbag and the auxiliary airbag depending on a pre-crash case where a high-speed side collision is expected and a normal case where a low-speed side collision is expected or the measurement value is erroneous. | 02-09-2012 |
20120043740 | Curtain Airbag Cushion and Curtain Airbag Module Using the Same - Disclosed herein is a curtain airbag cushion. The cushion has a length appropriate for being deployed to the chest of a passenger. A blocking part which partitions the interior of the cushion into portions is oriented in the vertical direction. The lower end of the blocking part is spaced apart from the bottom of the cushion by a predetermined distance. Thus, when an inflator explodes, gas discharged from the inflator is guided towards the lower portion of the cushion and then guided towards the front or upper portion of the cushion through the space between the lower end of the blocking part and the bottom of the cushion. | 02-23-2012 |
20120123645 | PASSENGER-SHIFT AIRBAG APPARATUS, SIDE AIRBAG SYSTEM HAVING THE SAME, AND METHOD OF CONTROLLING SIDE AIRBAG SYSTEM - A passenger-shift airbag apparatus may include an inflator installed at a predetermined position in a seat back of a vehicle; and a passenger-shift airbag cushion fluid-connected to the inflator directly or by a gas supply tube, the passenger-shift airbag cushion being located in the seat back adjacent to a lateral side of the seatback, so that when the passenger-shift airbag cushion is inflated by gas supplied from the inflator, the passenger-shift airbag cushion shifts the passenger towards an inside of the vehicle. | 05-17-2012 |
20120248745 | SIDE AIRBAG FOR VEHICLES - A side airbag for a vehicle may include an inflator provided on a seat side frame in a seat of the vehicle, a first cushion part installed in a seat side pad mounted on the seat side frame, wherein the first cushion part covers the seat side frame and may be fluid-connected to the inflator so that when the inflator may be operated, the first cushion part inflates inside the seat side pad to push an occupant sideways, and a second cushion part integrally connected to the first cushion part so that when gas may be supplied from the inflator into the second cushion part via the first cushion part, the second cushion part protrudes out of the seat side pad to protect a side portion of a body of the occupant. | 10-04-2012 |
20130038045 | WIRELESS AIRBAG APPARATUS - A wireless airbag apparatus may include an airbag control unit (ACU) receiving a sensing signal from a collision sensor and having a first wireless communication unit, and an airbag module having a second wireless communication unit and a power supply circuit to transceive a signal with the wireless communication unit of the ACU, wherein the power supply circuit supplies operating power to an inflator in accordance with a deployment signal of the airbag module. | 02-14-2013 |
20130147167 | DUAL CHAMBER SIDE AIR BAG APPARATUS FOR VEHICLE - A dual chamber side air bag apparatus may include an inflator mounted to a side of a sheet bag frame in an outdoor direction, an air bag cushion fluid-connected to the inflator and including a first chamber and a second chamber mounted at a side of the sheet bag frame in the outdoor direction and fluid-connected to the inflator and the first chamber to protrude and develop toward a front of the sheet bag frame when the inflator may be activated, for protecting side surface of the upper body of the passenger, and a tedder having one end thereof fixed to the sheet bag frame, a mid portion thereof wrapping the first chamber, and the other end thereof sewing-coupled to the air bag cushion in a boundary of the first and second chambers to provide a directivity so that the first chamber develops toward the upper body of the passengers. | 06-13-2013 |
20130257027 | SIDE AIRBAG - A side airbag apparatus may include a main chamber that is provided on a side of a seat and aligned toward a door to be deployed theretoward when a vehicle collides, to protect a passenger from a side directional collision, an auxiliary chamber that is connected to a rear part of the main chamber to be fluid-communicated to each other, wherein the auxiliary chamber is provided on a side of the main chamber toward the inside of the seat to push the passenger toward the inside of the seat when the auxiliary chamber is deployed, and a volume control tether provided in the rear part of the main chamber, wherein both ends of the volume control tether are fixed to facing-inner walls of the main chamber, respectively to restrict a deployment width of the rear part of the main chamber. | 10-03-2013 |
Patent application number | Description | Published |
20140021566 | MAGNETIC DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a magnetic memory device and a method of fabricating the same. The device may include a magnetic tunnel junction including a lower magnetic structure, an upper magnetic structure, and a tunnel barrier interposed therebetween. The tunnel barrier may have a width greater than that of the lower magnetic structure. | 01-23-2014 |
20140024138 | METHOD FOR ETCHING METAL LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - The inventive concepts disclosed herein include, for instance, methods for etching a metal layer and methods for manufacturing a semiconductor device using the etched metal layer. A wafer including a metal layer and a mask layer on the metal layer may be loaded into a process chamber. An etching gas may be supplied into the process chamber to etch the metal layer exposed by the mask layer. After the etching process, the mask layer may be removed. The etching gas can include phosphorus (P) and fluorine (F). An RF power may be constantly or selectively supplied to the process chamber, or different levels of RF power can be selectively supplied. An etching gas can be supplied to the process chamber when the RF power is off or at a lower level. A surface activation gas can be supplied when the RF power is on or at a higher level. | 01-23-2014 |
20140124881 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge. | 05-08-2014 |
20140349413 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode. | 11-27-2014 |
20150194595 | MAGNETIC MEMORY DEVICES - A magnetic memory device may include a lower electrode on a substrate, a memory element on the lower electrode, an upper electrode on the memory element, and a protection spacer enclosing a portion of a side surface of the lower electrode and protruding laterally from the side surface of the lower electrode. The protection spacer may have a bottom surface that is positioned at a level higher than that of a bottom surface of the lower electrode. | 07-09-2015 |
Patent application number | Description | Published |
20130008867 | METHODS FOR MANUFACTURING MAGNETIC TUNNEL JUNCTION STRUCTURE - Methods for manufacturing a magnetic tunnel junction structure include forming a magnetic tunnel junction (MTJ) layer by sequentially stacking a first ferromagnetic layer, a tunnel insulation layer, and a second ferromagnetic layer on a substrate, forming a mask pattern on the MTJ layer, and etching at least a portion of the MTJ layer in an etching chamber using the mask pattern as an etch mask, wherein the etching of the at least a portion of the MTJ layer includes applying a RF source power to a first electrode of the etching chamber as first RF power in a first pulselike mode, and applying a RF bias power to a second electrode of the etching chamber as second RF power in a second pulselike mode. The second pulselike mode of the RF bias power has a different phase from the first pulselike mode of the RF source power. | 01-10-2013 |
20130146997 | MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H | 06-13-2013 |
20130149499 | MAGNETIC DEVICES AND METHODS OF MANUFACTURING THE SAME - Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas. | 06-13-2013 |
20130234267 | MAGNETIC DEVICE - A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure. | 09-12-2013 |
20140264672 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed. | 09-18-2014 |
Patent application number | Description | Published |
20090086525 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 04-02-2009 |
20090283763 | Transistors, semiconductor devices and methods of manufacturing the same - A transistor having a self-align top gate structure and methods of manufacturing the same are provided. The transistor includes an oxide semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The transistor further includes a gate insulating layer and a gate electrode, which are sequentially stacked on the channel region. Semiconductor devices including at least one transistor and methods of manufacturing the same are also provided. | 11-19-2009 |
20100085821 | Operation method of non-volatile memory - Example embodiments provide a method of operating a non-volatile memory in which the non-volatile memory may only be changed from a first state to a second state and may not be changed from the second state to the first state during a programming operation. | 04-08-2010 |
20110116297 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20110116336 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20140119096 | SEMICONDUCTOR MEMORY APPARATUS, PROGRAM METHOD AND SYSTEM - Disclosed are a semiconductor memory apparatus, and a program method and a program system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of a initial voltage magnitude and an initial voltage applying time in an incremental step pulse programming (ISPP) mode for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells. Therefore, even in the case of the worst cell, since the incremental step of the ISPP may be minimized, the writing time may be reduced, and further, unnecessary current consumption may be reduced. | 05-01-2014 |
20140153315 | SEMICONDUCTOR MEMORY APPARATUS, REFRESH METHOD AND SYSTEM - Disclosed are a semiconductor memory apparatus, and refresh method and system. The semiconductor memory apparatus includes: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells. Therefore, the refresh of the resistive memory is efficiently performed, and as a result, performance deterioration may be minimized, and a lifespan of the device may be extended. | 06-05-2014 |
20140177322 | SEMICONDUCTOR MEMORY APPARATUS, VERIFY READ METHOD AND SYSTEM - Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells. Therefore, data of the memory is discriminated by analyzing distribution of the digital code values to monitor a characteristic of a current memory cell array and read the data having reliability. | 06-26-2014 |
Patent application number | Description | Published |
20110173079 | BIDDING MANAGEMENT METHOD AND SYSTEM USING BIDDING ATTRIBUTE INFORMATION - Provided is a bid management method and system using bid attribute information. The bid management method may include receiving a bid request including bid attribute information of an advertisement listing, determining a display rank of the advertisement listing using the bid attribute information, and calculating a final bid amount of the advertisement listing based on the display rank of the advertisement listing. | 07-14-2011 |
20110208596 | METHOD AND SYSTEM FOR PROVIDING ADVERTISING IN WHICH THE BID PRICE PER UNIT TIME IS ADJUSTED IN ACCORDANCE WITH ADVERTISING TRAFFIC - A method and system for offering an advertisement by adjusting a bid price per unit time according to advertising traffic are provided. The advertisement offering method includes determining a bid price per unit time based on an average bid price input by an advertiser and advertising traffic, and determining a charge regarding the advertisement of the advertiser based on the bid price per unit time. | 08-25-2011 |
20110246288 | METHOD AND SYSTEM FOR MANAGING QUALITY OF ADVERTISED WEBPAGE - Disclosed is a method and system for managing quality of an advertising document. The method of managing document quality may include verifying a number of actual clicks corresponding to a number of clicks that may occur during a predetermined period with respect to at least one document that may exist on the Web, verifying a number of expected clicks corresponding to a number of clicks that may be expected to occur during the predetermined period with respect to the at least one document, and determining a quality management index by which quality of the at least one document may be numerically expressed based on the number of the expected clicks and the number of the actual clicks. | 10-06-2011 |
20110251901 | METHOD FOR AUCTIONING AND BILLING FOR SEARCH ADVERTISEMENT, SYSTEM, AND COMPUTER-READABLE RECORDING MEDIUM - A method, system, and computer-readable recording medium for holding an auction and imposing a charge in relation to a search advertisement are provided. The method includes receiving bid information related to the search advertisement from an advertiser calculating device, the bid information including a search keyword, a posted time of the search advertisement, and a bid price for the search advertisement, determining a posting position and/or a posting order of the search advertisement with respect to a predetermined time slot of the posted time of the search advertisement, based on the bid price corresponding to the time slot, and posting the search advertisement according to the determined posting position and/or the posting order for the predetermined time slot. | 10-13-2011 |
20110258191 | SYSTEM AND METHOD FOR PROVIDING SEARCH RESULTS BASED ON REGISTRATION OF EXTENDED KEYWORDS - Provided is a system and method providing a search result by registering an extended keyword. A search result providing system may include a registration keyword determining unit to determine whether a registration keyword is required to be additionally registered based on at least of information associated with a registration of an input keyword, and a registration keyword registration unit to additionally register the registration keyword associated with the input keyword. | 10-20-2011 |
20110264514 | BILLING METHOD AND SYSTEM THAT DETERMINES ADVERTISEMENT COSTS ACCORDING TO UNIT TIME - A charging method and system for determining an advertising cost according to a unit time are provided. The charging method includes checking a performance index numerically indicating performance of an advertisement; checking a priority index of a next-priority advertisement to the advertisement; and determining an actual charge per unit time of the advertisement based on the performance index, the priority index, and a predetermined weight. | 10-27-2011 |
20110282751 | METHOD AND SYSTEM FOR ADVERTISING USING MINIMUM INCREMENT BID - A method and system for providing an advertisement using a minimum incremental unit are provided. The advertisement providing method includes adjusting a minimum incremental unit based on an initial bid price, an input bid price, and a maximum bid price bid price during an auction. The minimum incremental unit includes a minimum value of increment to be included in a current input bid price in addition to a previously input bid price. | 11-17-2011 |
20120084140 | SYSTEM AND METHOD FOR ADJUSTING NUMBER OF ADVERTISEMENT INVENTORIES - Provided is a system and method for adjusting a number of advertisement inventories based on a competition factor. An advertisement inventory adjusting system includes a competition determining unit to determine a competition factor for a keyword, an advertisement inventory adjusting unit to dynamically adjust the number of advertisement inventories based on the determined competition factor, and a data storage medium to store advertisement inventories. A method that uses a processor to adjust a number of advertisement inventories includes determining a competition factor for a keyword advertisement with respect to a keyword, and dynamically adjusting, using the processor, the number of advertisement inventories based on the determined competition factor, in which the advertisement inventories refer to available areas to display the keyword advertisement. | 04-05-2012 |
Patent application number | Description | Published |
20120091461 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor display substrate and a method of manufacturing the same are provided. The thin film transistor substrate includes a gate electrode formed on a display substrate, an active layer formed on the gate electrode to overlap with the gate electrode and including polycrystalline silicon, a first ohmic contact layer formed on the active layer, a second ohmic contact layer formed on the first ohmic contact layer, and a source electrode and a drain electrode each formed on the second ohmic contact layer. | 04-19-2012 |
20130037813 | CRYSTALLIZATION METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR ARRAY PANEL - Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array. | 02-14-2013 |
20130146864 | THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode. | 06-13-2013 |
20140264350 | CRYSTALLIZATION METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR ARRAY PANEL - Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array. | 09-18-2014 |
Patent application number | Description | Published |
20100045668 | Apparatus and Method for 3D Packet Scale Down with Proxy Server in Mobile Environment - A mobile network capable of 3-Dimensional (3D) packet scale down includes a server, mobile station and proxy server. The proxy server includes an apparatus and method for 3-Dimensional (3D) packet scale down. The method includes receiving a 3D packet from a main server, generating a set of unit figures constituting a 3D image using a parameter of the received 3D packet, and increasing a size of a partial unit figure in the generated set of the unit figures, and generating a set of the same size as the generated set of the unit figures, by figures of less number than the generated set of the unit figures. | 02-25-2010 |
20110110522 | PAIRING METHOD AND APPARATUS FOR AD-HOC CONNECTION IN WIRELESS COMMUNICATION TERMINAL - A pairing method and an apparatus thereof for an ad-hoc connection in a wireless communication terminal are provided. In the method, an event duration that occurs according to user manipulation is measured. A pairing key is generated using the measured duration. A pairing procedure is performed with a counterpart terminal using the pairing key. | 05-12-2011 |
20120072926 | METHOD AND APPARATUS FOR CONSTRUCTING A WIDGET ENVIRONMENT - A method and apparatus construct a widget environment. The method converts an application programming interface (API) into an API call in a Web service format in response to identifying that the API that is not executable in a current device is called. The method transmits the API call in the Web service format to a remote device in which the API is executable. The method receives a result obtained from the API call being executed in the Web service format in the remote device. | 03-22-2012 |
20120166584 | APPARATUS AND METHOD FOR EXTENDING UPnP NETWORK AREA - An apparatus and method for extending a UPnP (Universal Plug and Play) network are provided. The method includes, registering, by a transmission-side remote access agent, a plurality of transmission channels for transmitting data; storing, by the transmission-side remote access agent, when an event request message is received from at least one UPnP apparatus located in a transmission-side network, access information regarding at least one UPnP apparatus included in the event request message; and converting, by the transmission-side remote access agent, the event request message to an event request message, which can be used in the registered transmission channels, and transmitting the converted event request message to a reception-side network. | 06-28-2012 |
20120173744 | WIRELESS CONNECTION METHOD AND APPARATUS USING IMAGE RECOGNITION IN MOBILE COMMUNICATION TERMINAL - A method and apparatus for wireless connection with an external device using image recognition in a mobile communication terminal is provided. In the method for wireless connection with an external device using image recognition in a mobile communication terminal, an image including network connection information is acquired by a camera. The network connection information is acquired by recognizing the image through an image recognition algorithm. The wireless connection with the external device is performed using the acquired network connection information. | 07-05-2012 |
20130019295 | METHOD AND SYSTEM FOR OPEN AUTHENTICATIONAANM PARK; Sung-JinAACI Yongin-siAACO KRAAGP PARK; Sung-Jin Yongin-si KRAANM Woo; Hong-UkAACI SeoulAACO KRAAGP Woo; Hong-Uk Seoul KRAANM Kim; Kwan-LaeAACI Suwon-siAACO KRAAGP Kim; Kwan-Lae Suwon-si KRAANM Kwon; Soon-HwanAACI Seongnam-siAACO KRAAGP Kwon; Soon-Hwan Seongnam-si KR - Methods and apparatus for authentication are provided. A token request is received at a Web server from a third-party Web server. The third-party Web server is authenticated at the Web server. A token is issued to the third-party Web server. A user is authenticated based on the token issued to the third-party Web server. A token approval request is sent to a resource owner. A token approval or non-approval is received from the resource owner through a predefined channel. | 01-17-2013 |
Patent application number | Description | Published |
20080238299 | NANODOT ELECTROLUMINESCENT DIODE OF TANDEM STRUCTURE AND METHOD FOR FABRICATING THE SAME - A nanodot electroluminescent diode is disclosed. The nanodot electroluminescent diode comprises a lower electrode, an upper electrode, and unit cells interposed between the electrodes, wherein the unit cells comprise a quantum dot electroluminescent layer and also include an organic layer and/or an inorganic layer in addition to the quantum dot electroluminescent layer. The disclosed nanodot electroluminescent diode provides high efficiency, stability, and high luminance, and mixed colors, multi-colors, full color, and white electroluminescence can be obtained. | 10-02-2008 |
20090045720 | Method for producing nanowires using porous glass template, and multi-probe, field emission tip and devices employing the nanowires - Disclosed herein is a method for producing nanowires, which features the use of a porous glass template in combination with a solid-liquid-solid or vapor-liquid-solid process for growing nanowires which are highly straight and have nanoparticles precisely arranged therein. The nanowires can be grown into composite structures of superlattices and hybrids by modulating the composition of the materials provided thereto. Also disclosed is the use of the nanowires in multi-probes, field emission tips, and devices. | 02-19-2009 |
20100051583 | METHOD FOR PREPARING POROUS MATERIAL USING NANOSTRUCTURES AND POROUS MATERIAL PREPARED BY THE SAME - Disclosed herein is a method for preparing a porous material using nanostructures. The method comprises the steps of producing nanostructures using a porous template, dispersing the nanostructures in a source or precursor material for the porous material, aligning the nanostructures in a particular direction, and removing the nanostructures by etching. According to the method, the size, shape, orientation and regularity of pores of the porous material can be easily controlled, and the preparation of the porous material is simplified, leading to a reduction in preparation costs. | 03-04-2010 |
20100127214 | METHOD OF PREPARING OXIDE-BASED NANOPHOSPHOR - A method of preparing oxide-based nanophosphor includes preparing a reaction mixture by dissolving reaction mixture components including a metal halide, an oleate, and a precipitation auxiliary compound in a solvent; irradiating the reaction mixture with microwave radiation to precipitate an oxide-based nanophosphor precursor; and sintering the oxide-based nanophosphor precursor. | 05-27-2010 |
20100201004 | CARBON/EPOXY RESIN COMPOSITION AND METHOD OF PRODUCING A CARBON-EPOXY DIELECTRIC FILM USING THE SAME - A carbon/epoxy resin composition and a method of producing a carbon-epoxy dielectric using the same. The carbon/epoxy resin composition includes about 45 volume percent (volume %) to about 50 volume % of an epoxy composition, the epoxy composition including a bisphenol-based epoxy compound and an alicyclic epoxy compound, based on a total volume of the carbon/epoxy resin composition, about 2.0 volume % to about 3.1 volume % of carbon black, based on a total volume of the carbon/epoxy resin composition, about 80 parts by volume to about 104 parts by volume of an acid anhydride-based curing agent, based on 100 parts by volume of the epoxy composition, and about 1 part by volume to about 3 parts by volume of a tertiary alkylamine-based curing catalyst, based on 100 parts by volume of the epoxy composition. | 08-12-2010 |
20110101303 | LIGHT-EMITTING DEVICE COMPRISING SEMICONDUCTOR NANOCRYSTAL LAYER FREE OF VOIDS AND METHOD FOR PRODUCING THE SAME - A light-emitting device including a semiconductor nanocrystal layer and a method for producing the light-emitting device are provided. The light-emitting device includes a semiconductor nanocrystal layer whose voids are filled with a filling material. According to the light-emitting device, since voids formed between nanocrystal particles of the semiconductor nanocrystal layer are filled with a filling material, the occurrence of a current leakage through the voids is minimized, which enables the device to have extended service life, high luminescence efficiency, and improved stability. | 05-05-2011 |