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Kwon, NY
James Kwon, Sunnyside, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110088231 | SHOWER CURTAIN FASTENER WITH INTEGRAL HOOK - A shower curtain fastener comprising: a body portion adapted to be coupled to a shower curtain rod and a shower curtain; and a hook portion formed integrally with the body portion, the hook portion having a first segment extending substantially vertically downward from the bottom section of the body portion and a second segment extending outwardly to receive items apart from the shower curtain. | 04-21-2011 |
James Kwon, Brooklyn, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100239729 | MULTI-EDGE BAKING PAN - The present invention is directed to a baking pan for baking brownies or other foods in which substantially each side of the baked good has a crisp edge, the pan comprising a removable bottom surface, a plurality of sidewalls comprising a plurality of sidewall segments, a plurality of towers joined to said bottom surface and rising therefrom and not touching any of the sidewalls, and a single baking cavity formed by the bottom surface, the plurality of sidewalls and the plurality of towers, wherein said towers and sidewalls define a plurality of baking compartments and a plurality of passages connecting said baking compartments. The present invention further relates to a method of baking brownies comprising providing the pan of the present invention, depositing a batter or food product into said baking cavity, baking the batter or food product, and forming a food item with crisp edges. | 09-23-2010 |
| 20100239736 | MULTI-EDGE BAKING PAN - The present invention is directed to a baking pan for baking brownies or other foods in which substantially each side of the baked good has a crisp edge, the pan comprising a bottom surface, a plurality of sidewalls comprising a plurality of sidewall segments, a plurality of towers joined to said bottom surface and rising therefrom and not touching any of the sidewalls, and a single baking cavity formed by the bottom surface, the plurality of sidewalls and the plurality of towers, wherein said towers and sidewalls define a plurality of baking compartments and a plurality of passages connecting said baking compartments. The present invention further relates to a method of baking brownies comprising providing the pan of the present invention, depositing a batter or food product into said baking cavity, baking the batter or food product, and forming a food item with crisp edges. | 09-23-2010 |
O-Mun Kwon, Troy, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090219030 | Methods and Systems for Detecting Rotor Field Ground Faults In Rotating Machinery - Embodiments of the invention can include methods and systems for detecting rotor field ground faults in rotating machinery. In one embodiment, a system can include a rotor of the rotating machine comprising a plurality of field windings substantially disposed therein and a stator of the rotating machine comprising a plurality of stator windings substantially disposed therein, with an air gap existing between the rotor and the stator. The system can include a high-impedance grounding circuit at least temporarily connected between the rotor and a ground. Additionally, the system can include an air gap flux probe positioned at least temporarily between the rotor and the stator for measuring a magnetic flux density generated in the air gap during operation of the rotating machine. Finally, the system can further include an analyzer in electrical communication with the air gap flux probe for receiving an output of the air gap flux probe. | 09-03-2009 |
| 20090243647 | Non-Invasive monitoring and diagnosis of electric machines by measuring external flux density - System and methods for monitoring electric machines are provided. A magnetic field associated with the electric machine is measured at one or more points external to the electric machine, wherein a respective magnetic field value is associated with each of the one or more points. The one or more measured magnetic field values are compared to one or more corresponding expected values, and a determination of whether a fault is present in the electric machine is made based at least in part on the comparison. | 10-01-2009 |
O Sung Kwon, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110070732 | METHOD OF SILICIDE FORMATION BY ADDING GRADED AMOUNT OF IMPURITY DURING METAL DEPOSITION - A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy. | 03-24-2011 |
O-Sung Kwon, Wappingers Fall, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090101979 | Methods of Forming Field Effect Transistors Having Stress-Inducing Sidewall Insulating Spacers Thereon and Devices Formed Thereby - Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode. | 04-23-2009 |
O-Sung Kwon, Wappingers, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110156110 | Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage - Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode. | 06-30-2011 |
Seok Joon Kwon, Niskayuna, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110190162 | METHOD OF NUCLEIC ACID DELIVERY INTO THREE-DIMENSIONAL CELL CULTURE ARRAYS - The invention is directed to a three-dimensional cell culture array comprising spatially-separated matrices attached to a solid support, wherein a plurality of said matrices encapsulate cells transfected with nucleic acids, method for the preparation of the array and methods reducing the expression of a target gene. | 08-04-2011 |
Sung Su Kwon, Elmhurst, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080282732 | Jewelry Method and Apparatus - A replaceable device or plate is provided, which can be inserted into an earring base. The devices or plates can be configured to substantially span an opening of an earring base while they are securely and removably attached to the earring base. The earring base may comprised of a substantially closed curve substantially surrounding a substantially central opening. The first device may include a designation, such as a letter, word or phrase, and a logo or symbol. The substantially closed curve may be substantially circular. | 11-20-2008 |
Unoh Kwon, Fishkill, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100187610 | SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE - A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO | 07-29-2010 |
Unoh Kwon, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110095379 | SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT - A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided. | 04-28-2011 |