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Kwon, CA
Arthur Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090154278 | MEMORY DEVICE WITH SELF-REFRESH OPERATIONS - An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh. | 06-18-2009 |
Bo Kwon, Santa Monica, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090055488 | METHOD AND SYSTEM FOR COMMUNICATING A LOCATION SELECTION ASSOCIATED WITH AN EVENT - The invention provides a communications system comprising an event server computer system, an event creation module on the event server computer system for permitting the creation of an event from an event host computer system over the network, and a storing module on the event server computer system for storing the event on the event server computer system, a transmissions module on the event server computer system for transmitting a signal relating to the event from a first computer system to a second computer system over a network, and a location selection module on the event server computer system for selecting at least one location from the event host computer system and associating the location with the event on the event server computer system. | 02-26-2009 |
| 20090055513 | METHOD AND SYSTEM FOR COMMUNICATING CARPOOL INFORMATION - The invention provides a communications system comprising a receiving module for receiving the carpool information from a plurality of user computer systems over a network, a carpool module for collecting carpool information received by the receiving module from a plurality of user computer systems, storing the carpool information at a server computer system, the carpool information being for a plurality of users corresponding to carpool information collected from the plurality of user computer systems at a server computer system, and permitting access to the carpool information collected from the plurality of user computer systems on the server computer system from each one of the user computer systems, the carpool information being associated with the event. | 02-26-2009 |
Chang-Ki Kwon, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090051391 | ADJUSTABLE INPUT RECEIVER FOR LOW POWER HIGH SPEED INTERFACE - A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance. | 02-26-2009 |
| 20090116602 | High speed, wide frequency-range, digital phase mixer and methods of operation - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 05-07-2009 |
| 20090219769 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 09-03-2009 |
| 20100194200 | Multiple Supply-Voltage Power-Up/Down Detectors - A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector. | 08-05-2010 |
| 20100271070 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 10-28-2010 |
| 20110156788 | HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 06-30-2011 |
Chulan Kwon, Burlingame, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100129915 | METHODS FOR INDUCING CARDIOMYOGENESIS - The present invention provides methods of inducing cardiomyogenesis and expansion of cardiac progenitors in a population of stem cells or progenitor cells, the methods generally involving inducing a canonical Wnt signaling pathway in the stem cells or progenitor cells. The present invention provides methods of generating a population of cardiomyocytes or cardiac progenitors from a population of stem cells or progenitor cells, the methods generally involving contacting the stem cells or progenitor cells with an agent that induces canonical Wnt signaling. A subject method is useful for generating a population of cardiomyocytes or cardiac progenitors, which can be used in research and therapeutic applications. | 05-27-2010 |
Dongheum Kwon, Anaheim, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080279991 | Egg Package Assembly - An egg package assembly includes a protective case that contains predetermined number of eggs and a sleeve that fixedly surrounds the protective case. The protective case comprises a base and a lid. The sleeve comprises a thin packing film that is shrunk by heat. The sleeve is provided having a length similar to that of the case and a width wider than that of the case. After heat shrinking, the sleeve conforms to the shape of the case and fixed to the case. The length of the sleeve shrinks and allows the ends of the case to be exposed. | 11-13-2008 |
Haesung Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080278849 | Flow balancer for track misregistration improvement - Disclosed is a hard disk drive that includes at least one disk enclosed by a cover and a disk. A damper is separated from the disk by an air gap about 1.0 mm. The damper and air gap reduce the velocity of the air flow and any vibration associated with the flow of air. | 11-13-2008 |
| 20080304178 | High-flow rate filter wall design - A hard disk drive that includes a disk, a head, and a filter enclosed by a base plate and a cover plate. The base plate has a filter wall with a fore end and an aft end. The fore end of the filter wall has a tapered surface that extends to an apex. The distal end of the filter wall has a first filter attachment portion separated from a second filter attachment portion by a groove. The second filter attachment portion may be longer than the first filter attachment portion. The filter wall induces a flow of air that inhibits particle attachment to a reverse side of the filter. | 12-11-2008 |
| 20080304183 | Flexure for head gimbal assembly with narrow gimbal width in a hard disk drive - A hard disk drive and head gimbal assembly including a flexure finger with a micro-actuator split of the flexure supporting a micro-actuator control line, leading to minimized gimbal width for the flexure finger about the micro-actuator assembly including the coupled slider and micro-actuators to reduce mechanical vibrations caused by wind off of a rotating disk surface accessed by the slider. | 12-11-2008 |
| 20090210206 | Method and for wide track erasure in a hard disk drive - A method and its implementation as a program system are disclosed herein for generating an air flow report based upon a cellular model of the air flow of a hard disk drive including a parameterized component approximated by a component parameter list and a map of the partitioned regions of the hard disk drive. The air flow report is generated based upon the cellular model and a partition/region map. The partition/region map lumps the simulation domain into a small number of regions and then calculates the fluxes across boundaries of the regions. These fluxes accumulate the results of many individual cells, averaging out small variations caused by rounding and/or the convergence properties of the specific cellular approach used. A simulation figure of merit is calculated from the air flow report that further refines the accuracy, effectively removing even more noise. | 08-20-2009 |
| 20100007987 | METHOD AND APPARATUS FOR DAMPENING AND FILTERING AIR FLOW EFFECTS IN A HARD DISK DRIVE - A hard disk drive is disclosed including at least one air filter mounted on a shroud wall of the base and at least two disk dampers where at least one disk damper covers a fraction of the maximal covering angle configured with the air filter to optimize both the air filter and disk dampening. Methods of manufacturing the hard disk drive are also disclosed. | 01-14-2010 |
| 20100067147 | METHOD AND APPARATUS FOR A HARD DISK DRIVE INCLUDING A BALANCED MICRO-ACTUATOR - This application discloses a hard disk drive, a head stack assembly, and a head gimbal assembly, each including a micro-actuator hinge configured to position a slider over a rotating disk surface with greater stroke sensitivity while reducing bending perpendicular to the disk surface. The micro-actuator hinge includes at least one micro-actuator, a hinge plate and at least one hinge plate cover, with the micro-actuator including a first region and a second region, each coupled between the hinge plate and the hinge plate cover. | 03-18-2010 |
| 20100188777 | METHOD AND APPARATUS FOR A DISK DAMPER INCLUDING AN ENCLOSING FLOW CHAMBER WALL FOR A HARD DISK DRIVE - A hard disk drive with a disk base including a disk wall with a first intake, a second intake off of the first intake, an outlet and an air filter configured to receive a first airflow from the first intake and suction from a second airflow from the second intake creating negative pressure at a trapping surface of the air filter away from the outlet. At least one disk rotates to create a rotating disk surface generating airflow configured to enter the first intake to create the first airflow. A disk damper includes an enclosing wall neighboring the air filter to create a flow chamber providing a third airflow through the outlet formed of the first air flow crossing the trapping surface and the second air flow. A disk cover mounts on the disk base to encapsulate the air chamber. The disk base and disk damper are disclosed. | 07-29-2010 |
| 20120087038 | PARTIAL RIBS IN DISK BASE TO STIFFEN A HARD DISK DRIVE - A hard disk drive and a disk base are disclosed with the disk base including a first face configured to form a disk cavity for the spindle motor, disk(s) and a voice coil motor and a second face configured to couple with a controller Printed Circuit Board (PCB) including at least one integrated circuit. Both faces are include a hub for mounting the spindle motor and surrounded by an outer wall. The first face and/or the second face include at least one partial rib extending from the hub or the outer wall partway to the other. The partial ribs are configured to position the integrated circuit and stiffen the disk base and hard disk drive from mechanical shocks, such as dropping the unit including the hard disk drive. A handheld device is disclosed including at least one of the disclosed hard disk drives with improved reliability to mechanical shocks. | 04-12-2012 |
Hancheol Kwon, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120103371 | METHOD AND APPARATUS FOR DRYING A SEMICONDUCTOR WAFER - A method and apparatus for drying semiconductor wafers uses hot isopropyl alcohol in liquid form at temperatures above 60° C. and below 82° C. The use of hot IPA better avoids pattern collapse and permits reduced consumption of IPA. The wafer temperature can be maintained by applying hot deionized water to the opposite wafer side and by evaporating the hot IPA from the wafer surface using heated nitrogen gas. | 05-03-2012 |
Hye-Sook Kwon, San Mateo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100330114 | Use of SIRT1 Activators or Inhibitors to Modulate an Immune Response - The present disclosure provides a method of increasing an immune response in an individual, the method involving administering to an individual in need thereof an inhibitor of SIRT1. The present disclosure provides a method of reducing an immune response, e.g., to treat chronic immune hyperactivity, the method generally involving administering to an individual in need thereof an activator of SIRT1. The present disclosure provides a method of modulating activation and differentiation of CD4 | 12-30-2010 |
Hyuck Jin Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110310691 | Multi-Port Memory Using Single-Port Memory Cells - A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle. | 12-22-2011 |
Hyukjoon Kwon, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120039406 | CHANNEL DESCRIPTION FEEDBACK IN A COMMUNICATION SYSTEM - In a method for estimating a channel between a transmitter and a receiver in a communication network, a plurality of training signal fields are received at the receiver. Each training signal field includes a plurality of orthogonal frequency division multiplexing (OFDM) tones, and the OFDM tones include at least a plurality of training data tones and one or more pilot tones. Channel estimate data corresponding to the plurality of training data tones and the one or more pilot tones is determined. Channel estimate data corresponding to only a subset of the OFDM tones or data generated using the channel estimate data corresponding to the subset of OFDM tones is transmitted to the transmitter, wherein the subset excludes pilot tones. | 02-16-2012 |
| 20120087426 | COMPRESSED FEEDBACK FORMAT FOR WLAN - In a method for transmitting channel feedback data from a receiver to a transmitter, channel data for a plurality of orthogonal frequency division multiplexing (OFDM) tones for one or more spatial streams corresponding to a communication channel is determined. A plurality of angle values associated with the one or more spatial streams and one or more OFDM tones is determined. For each of the one or more spatial streams, a per-tone signal to noise ratio (PT-SNR) associated with one or more OFDM tones is determined, and an average signal to noise ratio (avg-SNR) is determined by averaging the signal to noise ratio (SNR) values. A feedback report is generated to include at least i) the plurality of angle values, ii) the PT-SNRs, and iii) the avg-SNR. The feedback report is included in a data unit to be transmitted from the receiver to the transmitter. | 04-12-2012 |
Hyukjoon Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110310827 | ALTERNATE FEEDBACK TYPES FOR DOWNLINK MULTIPLE USER MIMO CONFIGURATIONS - A method in a communication network includes obtaining descriptions of a plurality of communication channels each communication channel associated with a different one of a plurality of receivers; and generating a plurality of steering vectors, one for each of the plurality of receivers, using the descriptions of the plurality of communication channels; wherein each steering vector is used to transmit data to a corresponding one of the plurality receivers via a plurality of antennas and over a corresponding one of the communication channels simultaneously and wherein each steering vector is used to communicate data on a different one of the plurality of communication channels, and wherein each steering vector is generated to reduce interference on a corresponding communication channel caused by simultaneous transmission of data on other communication channels. | 12-22-2011 |
Inchan Kwon, Pasadena, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110008828 | METHODS OF INCORPORATING AMINO ACID ANALOGS INTO PROTEINS - The invention provides a method of incorporating nonstandard amino acids into a protein by utilizing a modified aminoacyl-tRNA synthetase to charge the nonstandard amino acid to a modified tRNA, which forms strict Watson-Crick base-pairing with a codon that normally forms wobble base-pairing with natural tRNAs. | 01-13-2011 |
James Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110243142 | INGRESS AND EGRESS SWITCH WHICH DETERMINES SERVICES RELATED TO AN INCOMING PACKET - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
| 20110243143 | SWITCH WITH PACKET SERVICES PROCESSING - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
| 20110243144 | NETWORK ARCHITECTURE WITH DISTRIBUTION OF PACKET SERVICES TO VARIOUS SWITCHES - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
| 20110246899 | SIMPLIFIED DISTRIBUTION OF SOFTWARE TO NETWORKED DEVICES - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
Jinsu Kwon, Campbell, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090145645 | Interconnection element with posts formed by plating - An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed. | 06-11-2009 |
| 20090146303 | Flip Chip Interconnection with double post - A packaged microelectronic assembly includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each of the first posts has a width in a direction of the front surface and a height extending from the front surface, wherein the height is at least half of the width. There is also a substrate having a top surface and a plurality of second solid metal posts extending from the top surface and joined to the first solid metal posts. | 06-11-2009 |
| 20090148594 | Interconnection element with plated posts formed on mandrel - An interconnection element can be formed by plating a metal layer within holes in an essentially non-metallic layer of a mandrel, wherein posts can be plated onto a metal layer exposed within the holes, e.g., a metal layer covering the holes in the non-metallic layer. The tips of the posts can be formed adjacent to ends or bottoms of the blind holes. Terminals can be formed in conductive communication with the conductive posts. The terminals can be connected through a dielectric layer to the conductive posts. At least a portion of the mandrel can then be removed from at least ends of the holes. In this way, the tips of the conductive posts can become raised above a major surface of the interconnection element such that at least the tips of the posts project beyond the major surface. | 06-11-2009 |
| 20110074027 | FLIP CHIP INTERCONNECTION WITH DOUBLE POST - A microelectronic assembly includes a substrate having a first surface, a plurality of first conductive pads exposed thereon, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to one of the conductive pads. Each metal post extends along a side wall from the base to ends remote from the conductive pad. The assembly further includes a dielectric material layer having a plurality of openings and extending along the first surface of the substrate. The first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries thereof. Fusible metal masses contact the ends of some of first metal posts and extend along side walls towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically can be connected the conductive pads. | 03-31-2011 |
Jungtae Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100259964 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 10-14-2010 |
| 20110122687 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 05-26-2011 |
Kitae Kwon, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120127651 | Systems and Methods for Securing Mobile Computing Devices - Systems for securing mobile devices such as laptops are provided. Such systems are characterized by two end members, each with a male electrical connector, that engage opposite sides of mobile device, a crossbeam between the two end members that cradles the underside of the mobile device, and a mechanical linkage that is used to release the mobile device. In addition to a slim form factor, systems of the present invention can comprise registration posts to align a top edge of the mobile device to the crossbeam, a receptacle for a power adapter connector, and a locking mechanism to lock an end member to the crossbeam and optionally also lock the power adapter connector to the system. | 05-24-2012 |
Kookhwan Kwon, San Ramon, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090237109 | Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus - A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance. | 09-24-2009 |
Mike Kwon, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110228765 | TELEPHONY TERMINAL - Methods and apparatus implementing a telephony terminal for connecting a telephone to a data network. In one implementation, a telephony system includes: a phone connection for connecting to a telephone; a network connection for connecting to a network; and a controller connected to said phone connection and to said network connection; wherein said controller provides a phone service for processing information for said phone connection, said controller provides a network service for processing information for said network connection, and said controller provides a network voice service for converting information to and from a network voice format. | 09-22-2011 |
Oh-Hoon Kwon, Burbank, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110284744 | METHOD AND SYSTEM FOR 4D TOMOGRAPHY AND ULTRAFAST SCANNING ELECTRON MICROSCOPY - A 4D electron tomography system includes a stage having one or more degrees of freedom, an electron source, and electron optics operable to direct electron pulses to impinge on a sample supported on the stage. A pulse of the electron pulses impinges on the sample at a first time. The system also includes a laser system and optics operable to direct optical pulses to impinge on the sample. A pulse of the optical pulses impinges on the sample at a second time. The system further includes a detector operable to receive the electron pulses passing through the sample, a controller operable to independently modify an orientation of the stage and at least one of the first time or the second time, a memory operable to store sets of images, and a processor operable to form a 4D tomgraphic image set from the sets of images. | 11-24-2011 |
Ohkyung Kwon, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090163285 | In-field behavior recording device for golf putting - The present invention relates generally to the field of behavior sensing and recording device. More specifically, the present invention is to measure and record full motion related signals on a part of putter. | 06-25-2009 |
Ohyun Kwon, Los Angeles, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100063114 | INHIBITORS OF PROTEIN PRENYLTRANSFERASES - The present invention is directed to novel compounds. These compounds can be useful in inhibiting the activity of GGTase I. The compounds can also be used as anti-cancer therapeutics including as part of methods for treating cancer, in assays, and in kits. | 03-11-2010 |
| 20110178138 | INHIBITORS OF PROTEIN PRENYLTRANSFERASES - The present invention is directed to novel compounds. These compounds can be useful in inhibiting the activity of protein prenyltransferases including GGTase I and/or RabGGTase. The compounds can also be used as anti-cancer therapeutics including as part of methods for treating cancer, in assays, and in kits. | 07-21-2011 |
Sunghoon Kwon, Albany, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100171950 | METHODS FOR UNIFORM METAL IMPREGNATION INTO A NANOPOROUS MATERIAL - The methods, systems | 07-08-2010 |
Sung Yun Kwon, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090035446 | Solid Solution Perforator Containing Drug Particle and/or Drug-Adsorbed Particles - A solid drug solution perforator containing drug particles and/or drug-adsorbed or loaded particles with an associated drug reservoir (SSPP system) are provided for delivering therapeutic, prophylactic and/or cosmetic compounds, diagnostics, and for nutrient delivery and drug targeting. For drug delivery, the SSPP system includes an active drug ingredient in particulate form or drug adsorbed on the particle surface in a matrix material that dissolves upon contact with a patient's body. In a preferred method of transdermal drug delivery, an SSPP system containing a drug-adsorbed microparticle penetrates into the epidermis or dermis, and the drug is released from the (dissolving) SSPP system perforator and desorbed from the particles. An additional drug is optionally delivered from a patch reservoir through skin pores created by insertion of the perforator Formulation and fabrication procedures for the SSPP and associated reservoir are also provided. An SSPP system can be fabricated with variety of shapes and dimensions. | 02-05-2009 |
| 20090060986 | Transdermal delivery systems - Disclosed are bupivacaine transdermal delivery systems, and related methods. | 03-05-2009 |
| 20100010031 | TRANSORAL DOSAGE FORMS COMPRISING SUFENTANIL AND NALOXONE - The invention pertains to methods that include administering to a subject a transoral dosage form comprising a pharmaceutical carrier and sufentanil, and maintaining a mean pH ranging from about 3.5 to about 5.5 during a dosing period after administration of the transoral dosage form as determined using an in vitro donor media test. Related dosage forms are also disclosed. Also disclosed are transoral dosage forms and related methods, wherein a transoral dosage form may comprise: (1) about 5 to about 1000 micrograms of sufentanil; (2) about 50 micrograms to about 100 milligrams of naloxone; and (3) acidifying material in an amount sufficient to provide a mean pH ranging from about 3.5 to about 5.5 during a dosing period after administration of the transoral dosage form as determined using an in vitro donor media test; wherein the dosing period begins no earlier than about 1 minute after administration of the transoral dosage form, and ends no later than about 120 minutes after administration of the transoral dosage form. | 01-14-2010 |
| 20110121486 | METHOD OF MANUFACTURING SOLID SOLUTION PEFORATOR PATCHES AND USES THEREOF - Methods for fabricating and manufacturing solid solution perforators (SSPs) using sharp metal or glass needles and/or subsequent molding and use are described. The methods entail making microneedles by various precision machining techniques and micromold structures from curable materials. Various designs of patch, cartridge and applicator are described. Also described are methods for adjusting the microneedle mechanical strength using formulation and/or post-drying processes. | 05-26-2011 |
Taewoo Kwon, Burlingame, CA US
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|---|---|---|
| 20110070658 | SYSTEMS AND METHODS FOR DETERMINING THE PERCENTAGE OF GLYCATED HEMOGLOBIN - Described herein are systems and methods for assaying a sample to quantitatively determine the percentage of glycated hemoglobin in the sample. | 03-24-2011 |
Taewoo Kwon, Oakland, CA US
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|---|---|---|
| 20100227311 | TISSUE CULTURE SYSTEM FOR PRODUCTION OF HEPATITIS C VIRUS - A tissue culture system for production of infectious hepatitis C virus is described. In particular, the invention provides recombinant monocistronic and bicistronic genomic constructs for production of virus, including constructs for production of wild-type HCV type 2 | 09-09-2010 |
Thomas D. Kwon, Irvine, CA US
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|---|---|---|
| 20100033359 | NONLINEAR COMPENSATION IN ANALOG TO DIGITAL CONVERTERS - An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor. | 02-11-2010 |
| 20100060496 | MINIMIZING ADVERSE EFFECTS OF SKEW BETWEEN TWO ANALOG-TO-DIGITAL CONVERTERS - Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal. | 03-11-2010 |
Thomas J. Kwon, Dublin, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110095258 | MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first cross-sectional area, coupled to a reversible resistivity switching material, such as aC, having a region that has a second cross-sectional area smaller than the first cross-sectional area. | 04-28-2011 |
Tom Kwon, San Pedro, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100067729 | Sing-along stand with performance interface configured to display a music storage/playback device - A microphone speaker system includes a base having a speaker, a stand extending between a first end and a second end, the first end coupled to the base, a performance interface coupled to the second end of the stand, and a microphone support coupled to the performance interface. The performance interface is configured to removably retain a music storage/playback device that electrically connects with the speaker through the base. The microphone support is coupled to the performance interface and configured to adjustably support a microphone that electrically connects with the speaker through the base. | 03-18-2010 |
Yoon H. Kwon, Mission Viejo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110028995 | Surgical Puncture Cinch and Closure System - A system for forming a purse string suture, including a suture applicator having a proximal handle having a suture spool mounted thereon or in an internal chamber. A length of suture is partly wound on the spool, and a hollow suture needle extends from a distal end of the handle and contains a free end of the length of suture. The suture needle projects distally from the handle in a helical shape and terminates in a sharp distal tip with an opening in one side close to the distal tip. The free end of the length of suture may extend out of the distal tip and back into the hollow suture needle through the opening. The suture needle may have a deflection segment adjacent the distal tip that is more flexible than the rest of the helical distal portion of the suture needle. A linear hollow pivot shaft extends from a distal end of the handle substantially along an axis of the helical distal portion of the suture needle. The pivot shaft has a blunt tip with a substantially larger radial profile than the shaft to prevent puncturing tissue. | 02-03-2011 |
Young Kwon, Thousand Oaks, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110189964 | METHOD AND APPARATUS FOR PROVIDING IMPEDANCE MATCHING FOR HIGH-FREQUENCY SIGNAL TRANSMITTER - In accordance with another representative embodiment, a high-frequency signal transmitter a power amplifier configured to supply a high-frequency signal; an antenna configured to transmit the high-frequency signal; a transmission line configured to transfer the high-frequency signal from the power amplifier to the antenna; and an impedance matching circuit connected to the transmission line. The high-frequency signal transmitter also comprises a mismatch detector. The mismatch detector is configured to designate a comparatively poor linearity region and a comparatively good linearity region by dividing a Smith chart into the two regions based on Adjacent Channel Power Ratio (ACPR) contours drawn on the Smith chart at a point on the transmission line where the impedance matching circuit is connected, to measure a time-dependent reflection coefficient of the high-frequency signal transmitter in terms of a phase and a magnitude, to determine whether the reflection coefficient is located in the comparatively poor linearity region or the comparatively good linearity region, and based on a result of the determination, to improve the linearity of the high-frequency signal transmitter. | 08-04-2011 |
| 20110234316 | IMPEDANCE MATCHING CIRCUIT CAPABLE OF EFFICIENTLY ISOLATING PATHS FOR MULTI-BAND POWER AMPLIFIER - In accordance with a representative embodiment, an impedance matching circuit for use at an output stage of a power amplifier is disclosed. The impedance matching circuit comprises: an input port for receiving a frequency band signal; and a plurality of paths, each path being allocated with a principal band signal to be transmitted therethrough and including a path on-off network and a fixed-value impedance matching network. Depending on a type of the received frequency band signal, the path on-off network is configured to activate a selected one of the plurality of paths by rendering an input impedance of the selected path to have a lower absolute magnitude so that the signal is transmitted therethrough, and to deactivate the remaining paths of the plurality of paths by rendering the input impedance thereof to have a higher absolute magnitude so that the signal is not transmitted therethrough. The fixed-value impedance matching network matches a load impedance of the output port of each path to the input impedance thereof, thereby rendering the input impedance thereof to have a prescribed reference value with respect to the principal band signal when said path is activated by the path on-off network. | 09-29-2011 |
Young Kwon, Thousang Oaks, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110001576 | POWER AMPLIFIER MODULE - A power amplifier module comprises a power amplifier disposed in a coreless substrate and a directional coupler disposed in a coreless substrate and connected to the power amplifier. | 01-06-2011 |
Young Chul Kwon, Granada Hills, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080277017 | Degreasing Cloth - A degreasing cloth includes a ground thread woven on a first surface, that forms a plurality of closely-spaced holes, and a plurality of pile threads of a predetermined length extending from the first surface. Each of the pile threads is inserted and bound to the ground thread and comprises a loop. The thickness of the ground thread is substantially thicker than the thickness of the pile thread. The ground thread forms a mesh. The mesh comprises a pattern of hexagonal lattice. The greasing cloth may be formed into various applications including a pot cleaner and a laundry bag. The degreasing cloth goes under tenter process to give strength and roughness. | 11-13-2008 |
| 20090277059 | Bi-color Illuminated Emblem - A bi-color illuminated emblem includes a metal-look portion having a metal look layer, a substrate layer that supports the metal look layer, and a plurality of illuminating elements. The metal look layer and the substrate layer pass light from the illuminating elements. The illuminating elements emit light within a predetermined emission angle, which is 120 degree. The substrate layer is made of semi-transparent ABS. The substrate layer comprises an outer surface which supports the metal look layer, and an inner surface that faces the illuminating elements and has coarse texture that causes scattering of light. The distance between the inner surface of the substrate layer and the illuminating elements is in a range from 7˜10 mm. The illuminating element comprises an LED and a light guiding element that guides the light from the LED emits throughout and within the predetermined angle. | 11-12-2009 |
| 20100073946 | Bi-color Illuminated Wheel Emblem - A bi-color illuminated wheel emblem includes a rotating part that rotates together with the wheel, a stationary part that remains stationary when the automobile is moving, a bi-color illuminated display that is attached to the stationary part and an electric power supply. The rotating part comprises a mounting device that mounts the emblem to the wheel and a shaft that holds the stationary part rotatably. The stationary part comprises a hollow shell that is held by the shaft and a weight that is attached to the shell. The bi-color illuminated display comprises a metal look layer, illuminating elements and a light diffusion layer that diffuses light from the illuminating elements. The electric power supply comprises a stator that is attached to the stationary part and a rotor that is attached to the rotating part. | 03-25-2010 |
| 20110084610 | Bi-color License Plate Frame - A bi-color license plate frame, for surrounding a license plate of a vehicle, comprises a rectangular body comprising an aperture that is adapted to show a license plate, and a wall defining a hollow frame space inside the wall, a plurality of light-emitting elements contained in the frame space, and a controller that is electrically connected to the light-emitting elements and that controls the light intensity of the light-emitting elements according to the braking status of the vehicle. The wall of the rectangular body is translucent to the light of the light-emitting elements, and comprises a light diffusion layer, whereby surface illumination is provided when the light-emitting elements are turned on. Bi-color may include metal look and color emitted by the light-emitting elements, or red or black color of the light-diffusion layer and color emitted by the light-emitting elements. | 04-14-2011 |
Young-Do Kwon, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120013005 | Packaging Structure and Method - A method of making a semiconductor device includes providing a substrate and forming a conductive layer on the substrate. The conductive layer includes a first metal. A semiconductor die is provided. A bump is formed on the semiconductor die. The bump includes a second metal. The semiconductor die is positioned proximate to the substrate to contact the bump to the conductive layer and form a bonding interface. The bump and the conductive layer are metallurgically reacted at a melting point of the first metal to dissolve a portion of the second metal from an end of the bump. The bonding interface is heated to the melting point of the first metal for a time sufficient to melt a portion of the first metal from the conductive layer. A width of the conductive layer is no greater than a width of the bump. | 01-19-2012 |
Youngeun Kwon, Livermore, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100292104 | Photoswitchable Method for the Ordered Attachment of Proteins to Surfaces - Described herein is a method for the attachment of proteins to any solid support with control over the orientation of the attachment. The method is extremely efficient, not requiring the previous purification of the protein to be attached, and can be activated by UV-light. Spatially addressable arrays of multiple protein components can be generated by using standard photolithographic techniques. | 11-18-2010 |
Young Jik Kwon, Irvine, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090145758 | DEGRADABLE POLYACRYLAMIDE GEL - A degradable polyacrylamide gel for analyzing or separating at least one macromolecule in a sample using electrophoresis includes a polyacrylamide cross-linked with at least one degradable cross-linker having a ketal or acetal group with the formula (I), wherein R | 06-11-2009 |
| 20090233359 | POLYMERS AND COMPLEXES FOR DELIVERY OF NUCLEIC ACIDS TO INTRACELLULAR TARGETS - A complex includes a nucleic acid and a cationic polymer with at least one side chain coupled to the nucleic acid. The at least one side chain including an acid degradable amine-bearing ketal or acetal linkage. | 09-17-2009 |
| 20110104661 | DEGRADABLE POLYACRYLAMIDE GEL - A degradable polyacrylamide gel for analyzing or separating at least one macromolecule in a sample using electrophoresis includes a polyacrylamide cross-linked with at least one degradable cross-linker having a ketal or acetal group with the formula (I), wherein R | 05-05-2011 |
Youngwoo Kwon, Thousand Oaks, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090309656 | MULTIPLE OUTPUT POWER MODE AMPLIFIER - A multi-mode power amplifier and an electronic device including the amplifier are described. | 12-17-2009 |