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Kwok, CA
Anna Kwok, Union City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100122154 | METHOD AND SYSTEM FOR GENERATING AND UTILIZING PERSISTENT ELECTRONIC TICK MARKS - Consistent with embodiments of the invention, computer-based systems and methods for annotating documents with a special type of graphical icon—referred to herein as a tick mark—are provided. Accordingly, utilizing a document annotation tool consistent with one embodiment of the invention, a user can quickly and easily place a tick mark next to an element of a document (e.g., a word, sentence, paragraph, number, chart, graph or figure) being displayed to visually convey some information about that particular element of the document. A second user, who is viewing the same document subsequent to the first user placing the tick mark, will immediately recognize and appreciate the information conveyed by the placement of the tick mark. | 05-13-2010 |
Annette K. Kwok, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090263322 | OCTAHYDRO-INDOLIZINE AND QUINOLIZINE AND HEXAHYDRO-PYRROLIZINES - The invention features substituted fused bicyclic compounds, pharmaceutical compositions containing them, and methods of using them to treat or prevent histamine-mediated diseases and conditions. | 10-22-2009 |
Cheni Kwok, San Mateo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100215727 | STABILIZED PICOPLATIN DOSAGE FORM - Methods for stabilizing aqueous solutions of picoplatin are provided. Such stable, preferably aseptic solutions are particularly useful for preparing unit dosages of picoplatin for oral or intravenous administration, preferably in combination with at least one additional non-platinum anti-cancer agent. | 08-26-2010 |
| 20100310661 | ORAL FORMULATIONS FOR PICOPLATIN - The invention provides formulations for the organoplatinum anticancer drug picoplatin. Self emulsifying compositions, stabilized nanoparticulate compositions, solid dispersions, and nanoparticulate suspensions in oils are provided, along with methods for preparation of the formulations. The formulations can provide improved oral availability of picoplatin relative a to a simple solution of picoplatin such as in water or normal saline solution and can be used in combination therapy. | 12-09-2010 |
Cheni Kwok, Burlingame, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100260832 | COMBINATION THERAPY FOR OVARIAN CANCER - The present invention provides a method to treat ovarian cancer by the administration of effective amounts of picoplatin and doxorubicin. | 10-14-2010 |
Chi Kong Kwok, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110064970 | COMPOSITE LUBRICANT FOR HARD DISK MEDIA - A composite lubricant for recording disk media, a recording disk media including a layer of the composite lubricant, and method of manufacturing the same are described. The composite lubricant may include a non-phosphazene component and a phosphazene component where the non-phosphazene component is a difunctional perfluoropolyether compound terminated with first and second polar end groups, the first polar end group comprising a first number of hydroxyls and the second polar end includes a second number of hydroxyls, greater than the first number of hydroxyls. The phosphazene component may be a difunctional perfluoropolyether compound terminated with a phosphazene functional group and with a third polar end group, the third polar end group comprising a third number of hydroxyls equal to the second number of hydroxyls. | 03-17-2011 |
Connie S. Kwok, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110033517 | COATINGS FOR IMPLANTABLE MEDICAL DEVICES COMPRISING HYDROPHILIC SUBSTANCES AND METHODS FOR FABRICATING THE SAME - A segmented polyurethane and an amphiphilic random or block copolymer are disclosed. The segmented polyurethane and the amphiphilic random or block copolymer can be used for fabricating a coating for an implantable medical device such as a stent. | 02-10-2011 |
David W. Kwok, La Mirada, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090159110 | THERMOELECTRIC GENERATION SYSTEM - A thermoelectric generation system for turbine engines and the like has at least one thermoelectric generator disposed proximate the turbine engine such that waste heat from the turbine engine can be converted into electricity. Vehicle performance and efficiency can be enhanced by mitigating the need for mechanically driven electric power generators, which undesirably drain power from the turbine engine thus adversely affect the vehicle's performance. | 06-25-2009 |
| 20090314879 | HYBRID THERMAL AIRSHIP - An airship comprises a shell, a gas storage system, an air storage system, a cargo storage system, a heating system, and a propulsion system. The shell encompasses a volume. The gas storage system is located within the volume, wherein the gas storage system is capable of storing a lighter than air gas. The air storage system is located within the volume, wherein the air storage system is capable of storing heated air. The heating system is capable of heating air. The propulsion system is capable of propelling the shell during flight. | 12-24-2009 |
| 20110108080 | THERMOELECTRIC GENERATOR ASSEMBLY AND SYSTEM - A thermoelectric generator assembly may comprise a frame that may include a first frame member and a second frame member. The first frame member and the second frame member are adapted to retain one or more thermoelectric generator devices in position therebetween for transferring heat energy through the one or more thermoelectric generator devices from a heat source to a heat sink to generate electrical energy. The thermoelectric generator assembly may also include a spacer positioned between the first frame member and the second frame member. A power bus may be included to provide the electrical energy generated by the one or more thermoelectric generator devices for powering an electrical device. | 05-12-2011 |
Derek Kwok, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120005885 | APPARATUS AND METHOD FOR STACKING FUEL CELLS - An apparatus for fuel cell stacking includes an assembly jig having a base; an alignment assembly configured to be engaged with the base; and a compression assembly configured to be engaged with the alignment assembly. | 01-12-2012 |
| 20120009493 | COMPRESSION OF DIRECT METHANOL FUEL CELL STACKS WITH CATALYST COATED MEMBRANES AND MEMBRANE ELECTRODE ASSEMBLY - An apparatus to control a swelling of a catalyst coated membrane in a fuel cell includes an insulator layer provided at a perimeter of the fuel cell. The insulator layer has a plurality of insulator films and is secured to a flow field plate. The insulator layer has a less compressibility relative to a gasket used in the fuel cell. A method for controlling a swelling of a catalyst coated membrane in a fuel cell includes providing an insulator layer at a perimeter of each of fuel cells in a fuel cell stack. The fuel cell stack is compressed for a predetermined duration when the catalyst coated membrane is in a substantially dry state. Passage of fuel is allowed inside the fuel cell thereby facilitating the catalyst coated membrane to swell. A swollen catalyst coated membrane is allowed to contact the insulator layer. | 01-12-2012 |
| 20120009495 | CONCENTRATION SENSOR USING AN ELECTROLYTIC CELL FOR AQUEOUS HYDROCARBON FUEL - A concentration sensor assembly for measuring a concentration of a aqueous hydrocarbon fuel to be supplied to a fuel cell stack, the assembly including a membrane electrode assembly having an anode, a cathode and an electrolyte membrane located between the anode and the cathode; a first monopolar flow field plate provided near the anode; a second monopolar flow field plate provided near the cathode; and a liquid gas separator. | 01-12-2012 |
Derek Kwok, San Leandro, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090004536 | Direct methanol fuel cell process tower - A direct methanol fuel cell integrated process assembly is provided. The assembly includes a housing, a fuel mixing/surge tank and an air/liquid separator integrated to the housing. A vent of the mixer/surge tank is at least proximal to a vent of the separator. The housing further includes at least one condensation pathway integrated along the housing, where the pathway enables exhaust condensates to return to the assembly. At least one exhaust port is provided, which vents directly to a cooling airstream to facilitate exhaust removal. A manifold is also provided, with the fuel valve, a water valve, a fuel pump and a water pump integrated with the housing, where the integrated process assembly reduces an amount of plumbing between the a liquid volume in the mixer and the separator. Further, a water volume of the process assembly is reduced and a form factor of the process assembly is also reduced. | 01-01-2009 |
Edward C. Kwok, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100125330 | SYNTHETIC VASCULAR PROSTHESIS AND METHOD OF PREPARATION - A biocompatible small-diameter vascular graft, blood vessels conduit, or cell growth stimulator carrier composition which includes a completely biodegradable, hydrophilic non-gel material that has a controllable blood absorption or other biological liquid absorption ability, a controllable fiber architecture and pore sizes, and other biologically active properties, such as cell adhesion, proliferation and spreading, haemostatic and vascular tissue growth acceleration. The material retains its contour and shape when wet, and does not exhibit any swelling. | 05-20-2010 |
Jason Kwok, Anaheim, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100234853 | DEVICE AND METHOD FOR DEFLATION AND REMOVAL OF IMPLANTABLE AND INFLATABLE DEVICES - A deflation device including a catheter having a proximal opening at a proximal end and a distal opening at a distal end; and a coring member disposed within the catheter and comprising a handle disposed near the proximal end of the catheter, a cable, and a coring tip disposed near the distal end of the catheter; wherein pressing said distal end of said catheter against said wall of said balloon creates a substantially normalized surface of said balloon relative to a coring tip and wherein the coring tip is a sharpened, hollow cylinder. A method for deflating and removing an implantable, inflatable device comprising: pressing a distal end of a catheter against the wall of an inflated balloon of an implanted device; advancing the coring tip within the catheter beyond the distal end of the catheter and into the balloon, whereby a hole adapted for advancing the catheter is created in the wall of the balloon; and advancing the catheter into the balloon. | 09-16-2010 |
Ka Kei Kwok, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100199244 | Formal Verification Of Clock Domain Crossings - Methods and apparatus for performing automated formal clock domain crossing verification on a device are detailed. In various implementations of the invention, a device may be analyzed, wherein the clock domain crossing boundaries are identified. Subsequently, a formal clock domain crossing verification method may be applied to the identified clock domain crossing boundaries, resulting in clock domain crossing assertions being identified. After which the identified assertions may be promoted for post clock domain crossing analysis. With various implementations of the invention, a formal clock domain crossing method is provided, wherein the device components near an identified clock domain crossing are extracted. Assertions may then be synthesized and verified based upon the extracted components. Various implementations of the invention provide for clock domain crossing verification to be performed iteratively, wherein a larger and larger selection of the device is extracted during formal verification. Additionally, various implementations of the present invention provide that the clock domain crossing verification operate on the fly during a device verification procedure. With further implementations, a bit-blasted approach to clock domain crossing verification may be provided during formal verification. | 08-05-2010 |
| 20100287524 | METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION - A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files. | 11-11-2010 |
Ka-Kei Kwok, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100242003 | Hierarchical Verification Of Clock Domain Crossings - The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation. Furthermore, in various implementations, the specific clock domain crossing verification checks employed during block level verification and top level verification are specified by a user of the implementation. | 09-23-2010 |
Kenneth Kwok, Irvine, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110181256 | Current Controlled Current Source, and Methods of Controlling a Current Source and/or Regulating a Circuit - Current sources, systems including the current source, and methods for regulating and/or controlling a circuit using the current source. The current source is generally configured to (i) receive a reference current, a bias voltage and a feedback/input current and (ii) provide an output current. The systems generally include the current source, a circuit directly or indirectly receiving the output current, a bias source/generator configured to provide the bias voltage, and a current reference configured to sink or source a predetermined amount of current from or to the output current. The method generally includes (a) applying a bias voltage to the current source, the current source receiving an input current and providing an output current; (b) sinking or sourcing a reference current from or to the output current; (c) applying the output of the current source directly or indirectly to a regulated circuit; and (d) providing the input current from the regulated circuit. | 07-28-2011 |
| 20110193542 | Thermally Controlled Driver/Switching Regulator, and Methods of Controlling and/or Regulating a Driver and/or Switching Regulator - The present invention provides circuits and methods for regulating and/or controlling integrated circuits such as drivers and switching regulators. The circuit generally includes a first switch configured to control or regulate a current, voltage drop or voltage boost; a first regulator or driver configured to transmit first pulses to the first switch, the pulses having a first pulse width; and pulse width modulation circuitry configured to (i) reduce the first pulse width when a first thermal threshold is met and (ii) increase the first pulse width when a second thermal threshold is met, the second thermal threshold being less than the first thermal threshold. | 08-11-2011 |
Kenneth C. Kwok, Irvine, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090273288 | LED DRIVER WITH DYNAMIC POWER MANAGEMENT - A light emitting diode (LED) system implements a LED driver to drive a set of one or more LED strings. The LED driver includes a voltage source to provide an adjustable output voltage to a head end of each LED string of the set for a first duration and a second duration following the first duration. The LED driver further includes a feedback controller to control the voltage source to adjust the output voltage for the second duration based on a digital code value generated from a minimum tail voltage of one or more tail voltages of the set at a sample point of the first duration. The LED driver further includes a power controller to temporarily enable one or more components of the feedback controller for a sample period of the first duration, the sample period comprising the sample point. | 11-05-2009 |
| 20100026203 | LED DRIVER WITH FRAME-BASED DYNAMIC POWER MANAGEMENT - Disclosed are example techniques for frame-based power management in a light emitting diode (LED) system having a plurality of LED strings. A voltage source provides an output voltage to drive the LED strings. An LED driver generates a frame timing reference representative of the frame rate or display timing of a series of image frames to be displayed via the LED system. An update reference is generated from the frame timing reference. The LED driver monitors one or more operating parameters of the LED system. In response to update triggers marked by the update reference, the LED driver adjusts the output voltage of the voltage source based on the status of each of the one or more monitored operating parameters (either from the previous update period or determined in response to the update trigger), thereby synchronizing the updating of the output voltage to the frame rate (or a virtual approximation of the frame rate) of the video being displayed. | 02-04-2010 |
| 20100156315 | LED DRIVER WITH FEEDBACK CALIBRATION - Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive a plurality of LED strings. An LED driver implements a feedback mechanism to monitor the tail voltages of the active LED strings to identify the minimum tail voltage and adjust the output voltage of the voltage source based on the lowest tail voltage. A loop calibration module of the LED driver calibrates the feedback mechanism of the LED driver based on a relationship between a digital code value used to generate a particular output voltage and another digital code value generated based on the minimum tail voltage resulting from the particular output voltage. | 06-24-2010 |
Leo Y. Kwok, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100319747 | Integrated Thermal Electric Generator with Heat Storage Unit - A multi-layered solid-state thermal-electrical generator (“MSTEG”) system capable of generating electricity from thermal energy is disclosed. An MSTEG system includes a thermal layer, a regulating layer, and a storage layer. The thermal layer, in one embodiment, includes multiple integrated thermal-electrical generator (“ITEG”) devices configured to generate electricity in response to a certain thermal condition. The thermal condition for example can be a temperature difference between 900° C. (Celsius) to 1200° C. for a certain layer. The regulating layer includes multiple thermal regulators deposited over the thermal layer, wherein the thermal regulators regulate temperature. The storage layer includes one or more thermal storage tanks deposited over the regulating layer, wherein each thermal storage tank is capable of storing heat. | 12-23-2010 |
Lily Kwok, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090105485 | HISTONE DEACETYLASE INHIBITORS - Compounds, pharmaceutical compositions, kits and methods are provided for use with HDAC that comprise a compound selected from the group consisting of: | 04-23-2009 |
| 20090111996 | HISTONE DEACETYLASE INHIBITORS - Compounds, pharmaceutical compositions, kits and methods are provided for use with HDAC that comprise a compound selected from the group consisting of: | 04-30-2009 |
| 20100063054 | cMET INHIBITORS - Compounds of the following formula are provided for use with cMET: | 03-11-2010 |
| 20100093767 | Mitotic Kinase Inhibitors - The invention relates to inhibitors of enzymes that disrupt the assembly and function of the mitotic spindle, compositions comprising the inhibitors of Formula (I), kits and articles of manufacture comprising the inhibitors and inhibitor compositions, and methods of using the inhibitors and inhibitor compositions. The inhibitors and inhibitor compositions are useful for treating, preventing or modulating diseases in which mitotic kinesins, including kinesin-like spindle protein (KSP), may be involved; symptoms of such diseases; or the effect of other physiological events mediated by mitotic kinesins, including KSP. | 04-15-2010 |
| 20100105665 | RENIN INHIBITORS - Compounds, pharmaceutical compositions, kits, article of manufacture, methods of using, and method of preparing of compounds having the formula of: | 04-29-2010 |
Pan Kwok, West Hills, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110282495 | MODULAR SEAT ACTUATION CONTROL SYSTEM AND COMMUNICATION METHOD - A seat actuation control system includes at least one seat having a plurality of seat devices and a plurality of control modules interconnected over a communication bus. Each module is associated with a corresponding seat control device and is configured to control its corresponding seat device. Each module includes a processor and a memory coupled to the processor and storing program instructions therein which include receiving a status packet from each of the other control modules over the communication bus, processing the status packet for updating the overall system status, and actuating the seat device based on the overall system status. The program instructions further include determining status of the corresponding seat device, generating a status packet including the status information, and broadcasting the status packet to the other modules over the communication bus. | 11-17-2011 |
Paul Kwok, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080225695 | FAILURE PROTECTION IN A PROVIDER BACKBONE BRIDGE NETWORK USING FORCED MAC FLUSHING - A technique for operating a network involves controlling the black-holing of traffic by forcing customer source MAC address (CMAC)-to-backbone source MAC address (BMAC) associations at provider backbone bridge (PBB) provider edge (PE) devices to be flushed from their corresponding forwarding information bases (FIBs) in response to a service failure so that new CMAC-to-BMAC associations, which are reflective of a secondary traffic path, are learned faster than they would otherwise be learned if the network had relied on native functionality to learn new CMAC-to-BMAC associations that are reflective of the secondary traffic path. | 09-18-2008 |
| 20080228943 | FAILURE PROTECTION IN A PROVIDER BACKBONE BRIDGE NETWORK USING SELECTIVE REDIRECTION - A technique for operating a network involves controlling the black-holing of traffic by selectively redirecting unicast traffic destined for a dual-homed customer equipment (CE) device from a first provider backbone bridge (PBB) provider edge (PE) device to a second PBB PE device in response to a service failure. Unicast traffic is selectively redirected from the first PBB PE device to the second PBB PE device for a time interval that is long enough to enable the customer source MAC address (CMAC)-to-backbone MAC address (BMAC) association of the second PBB PE device to be learned by other PBB PE devices. | 09-18-2008 |
Peter Kwok, San Ramon, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110299385 | NO SPLIT VIRTUAL CHASSIS BASED ON PASS THROUGH MODE - A method includes operating in a normal mode to receive and transmit packets, where the network device is one of multiple network devices that operate as a virtual chassis, where the virtual chassis corresponds to a single logical network device, and detecting when the network device crashes. The method further includes initiating a resetting process and operating in a pass through mode, during the resetting process, where the pass through mode permits packets to be received and transmitted to the network devices of the virtual chassis. | 12-08-2011 |
Pui-Yan Kwok, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090155780 | Methods for determining genetic haplotypes and DNA mapping - Improved methods of genetic haplotyping and DNA sequencing and mapping, including methods for making amplified ssDNA, methods for allele determination, and a DNA barcoding strategy based on direct imaging of individual DNA molecules and localization of multiple sequence motifs or polymorphic sites on a single DNA molecule. | 06-18-2009 |
Sai C. Kwok, Escondido, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090298415 | METHODS AND APPARATUS FOR POWER REDUCTION IN A TRANSCEIVER - An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied. | 12-03-2009 |
| 20100141233 | Switching Voltage Regulator With Frequency Selection - Techniques for mitigating interference from a switching voltage regulator by intelligently varying the switcher frequency of the switching voltage regulator are provided. In one aspect, the switcher frequency is set by adjusting a frequency setting input to a programmable clock divider. In a further aspect, a processor drives a programmable clock divider which receives a value representative of a dividing factor by which to divide a reference clock frequency signal to generate a desired switcher frequency for the switching voltage regulator. Values of the programmable clock divider are selectively varied to achieve optimal performance and mitigate the effect of switcher frequency spurious content for a given operating condition or conditions. | 06-10-2010 |
| 20100237951 | FREQUENCY CALIBRATION OF RADIO FREQUENCY OSCILLATORS - A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored. | 09-23-2010 |
Sai Chong Kwok, Escondido, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090068963 | COMMON MODE SIGNAL ATTENUATION FOR A DIFFERENTIAL DUPLEXER - Techniques for attenuating undesired signal components from a differential duplexer are described. The duplexer provides a differential received signal at RX+ and RX− ports. This differential received signal includes an undesired common mode signal, which may come from a transmit signal. The common mode signal is attenuated with a common mode trap in an impedance matching network coupled to the RX+ and RX− ports. The matching network includes a first passive circuit coupled between the RX+ port and a first node, a second passive circuit coupled between the RX− port and a second node, and the common mode trap coupled between the first and second nodes. In one design, the common mode trap includes a first inductor coupled between the first node and a common node, a second inductor coupled between the second node and the common node, and a capacitor coupled between the common node and circuit ground. | 03-12-2009 |
Shak Loong Kwok, Costa Mesa, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080294296 | Chip overheat protection - Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log. | 11-27-2008 |
Tyrone Kwok, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110304369 | METHOD FOR SOURCE SYNCHRONOUS HIGH-SPEED SIGNAL SYNCHRONIZATION - A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit. | 12-15-2011 |
| 20110310998 | SYSTEMS AND METHODS FOR PERFORMING PARALLEL DIGITAL PHASE-LOCKED-LOOP - A parallel phase locked loop (PLL) system includes a first chain of a plurality of pre-locking PLLs that operates from a free-run state to a locked state; and a second chain of a plurality of PLLs to work from the locked-state to recover signal output. | 12-22-2011 |
Wilfred W. Kwok, Markham, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100146162 | Apparatus and Method to Maximize Buffer Utilization in an I/O Controller - An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset. | 06-10-2010 |
William Kwok, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080281783 | SYSTEM AND METHOD FOR PRESENTING MEDIA - One embodiment of the present invention may permit retrieving and presenting media resources and/or providing online chat functionality. The embodiment may include a communication toolbar. The communication toolbar may be an interactive user tool that allows a user to retrieve and display document and media files, website/pages links, and/or conference links. The communication toolbar may also aid users in facilitating an on-line chat between one another. Another embodiment of the present invention takes the form of a media retrieval and display module that may show any and all retrieved search results to the user. Each search result may include a text description of the media record file, such as a title, a link to the media record file and a time bar associated with the media record file. The time bar may include at last one graphic indicator corresponding to a time in the media file where the search term is used. | 11-13-2008 |