Patent application number | Description | Published |
20080285353 | Flash memory device, method of manufacturing the same, and method of operating the same - Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region. | 11-20-2008 |
20090059671 | Method of programming non-volatile memory device - A method of programming a non-volatile memory device may include performing a first programming operation including applying a program voltage to a memory cell and verifying the memory cell using a first verification voltage. A perturbation pulse may be applied to the memory cell to facilitate thermalization of charges in the memory cell if the memory cell passes the verification using the first verification voltage. The memory cell may be verified using a second verification voltage greater than the first verification voltage after the perturbation pulse is applied. | 03-05-2009 |
20090067247 | Method of programming nonvolatile memory device - A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage. | 03-12-2009 |
20090078989 | Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device - Provided are a method of forming silicon nitride at a low temperature, a charge trap memory device including crystalline nano dots formed by using the same, and a method of manufacturing the charge trap memory device. The method of forming silicon nitride includes loading a substrate into a chamber of a silicon nitride deposition device comprising a filament; increasing a temperature of the filament to a temperature whereby a reactant gas to be injected into the chamber may be dissociated; and injecting the reactant gas into the chamber so as to form a crystalline silicon nitride film or crystalline silicon nitride nano dots on the substrate. In the method, the temperature of the filament may be maintained at 1,400° C.˜2,000° C., and a pressure in the chamber may be maintained at several to several ten torr when the reactant gas in injected into the chamber. | 03-26-2009 |
20090244980 | Method for reducing lateral movement of charges and memory device thereof - Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage. | 10-01-2009 |
20090251963 | Non-volatile memory device and method of manufacturing the same - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 10-08-2009 |
20090292972 | Error correction apparatus, method thereof and memory device comprising the apparatus - An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time. | 11-26-2009 |
20090292973 | Memory device and method of storing data - Memory devices and/or methods of storing memory data bits may be provided. A memory device may include a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it may be possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. | 11-26-2009 |
20090294633 | Image sensor using photo-detecting molecule and method of operating the same - Provided is an image sensor using a photo-detecting molecule and a method of operating the image sensor. The image sensor may include a plurality of first electrodes disposed parallel to each other and a plurality of second electrodes disposed parallel to each other in a direction perpendicular to the first electrodes and above the first electrodes, and a plurality of subpixels formed in regions where the first electrodes cross the second electrodes. Each of the subpixels may comprise a photo-detecting molecule layer that may generate charges by absorbing light having a certain wavelength, a charge generation layer that may form a plurality of secondary electrons by receiving the charges from the photo-detecting molecule layer when a known voltage is applied between the first electrodes and the second electrodes, and a variable resistance layer, an electrical state of which is changed by receiving the secondary electrons generated from the charge generation layer. | 12-03-2009 |
20100008136 | Methods of operating memory devices - Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying a first pass voltage to non-selected memory cells closest to the selected memory cell of the cell string; applying a second pass voltage to second closest non-selected memory cells to the selected memory cell; and applying a third pass voltage to other non-selected memory cells, where the first pass voltage is less than each of the second and third pass voltages and the second pass voltage is greater than the third pass voltage. | 01-14-2010 |
20100027351 | Memory device and memory programming method - A memory device and a memory programming method are provided. The memory device may program data in a multi-level cell (MLC) or a multi-bit cell (MBC) memory device. The memory device may include a memory cell array, a programming unit and a program level stabilization unit. The memory cell array may include a plurality of multi-level cells. The programming unit may be configured to program a first data page in the plurality of multi-level cells and to program a second data page in the plurality of multi-level cells having the programmed first data page. The program level stabilization unit may be configured to stabilize a program level of at least one of the first data page and the second data page. | 02-04-2010 |
20100044778 | Non-volatile memory device and method of manufacturing same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer. | 02-25-2010 |
20100044779 | Memory devices capable of reducing lateral movement of charges - Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell. | 02-25-2010 |
20100126584 | SOLAR CELLS AND SOLAR CELL MODULES - A solar cell module includes a solar cell provided at a center area of a support to expose an edge area of the support. An optical waveguide layer is provided on the edge area of the support to concentrate light to the solar cell. | 05-27-2010 |
20100172182 | Nonvolatile memory device and method for operating the same - Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells. | 07-08-2010 |
20100237312 | Nonvolatile memory device - The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor. | 09-23-2010 |
20100323509 | Nonvolatile semiconductor memory device and method of manufacturing the same - Provided is a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO | 12-23-2010 |
20110038197 | VARIABLE RESISTANCE MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A variable resistance memory array includes at least one variable resistance memory cell, wherein each variable resistance memory cell includes a well having a first type; and a cell structure on the well, the cell structure including a structure having a second type different from the first type and a variable resistance layer on the structure. | 02-17-2011 |
20110079839 | Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same - Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. | 04-07-2011 |
20110090744 | CHANNEL PRECHARGE AND PROGRAM METHODS OF A NONVOLATILE MEMORY DEVICE - A channel pre-charge method of a nonvolatile memory device including a cell string includes pre-charging a channel of the cell string according to a first word line bias condition and pre-charging the channel of the cell string according to a second word line bias condition, different than the first word line bias condition. | 04-21-2011 |
20110103154 | LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME - Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell. | 05-05-2011 |
20110169068 | NON-VOLATILE MEMORY DEVICES HAVING A FLOATING GATE CAP BETWEEN A FLOATING GATE AND A GATE INSULATING LAYER - Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern. | 07-14-2011 |
20110233610 | Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions - Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium. | 09-29-2011 |
20110233636 | Semiconductor Memory Device and Method of Manufacturing the Same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures. | 09-29-2011 |
20110233648 | Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 09-29-2011 |
20110312174 | Methods Of Manufacturing Three-Dimensional Semiconductor Devices - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 12-22-2011 |
20120043673 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate. | 02-23-2012 |
20120058629 | METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves. | 03-08-2012 |
20120155170 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 06-21-2012 |
20120280299 | Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same - Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other. | 11-08-2012 |
20130019143 | Memory Device And Method Of Storing Data With Error Correction Using Codewords - Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. | 01-17-2013 |
20130032875 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively. | 02-07-2013 |
20130092994 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region. | 04-18-2013 |
20130092998 | Memory Devices Capable Of Reducing Lateral Movement Of Charges - Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell. | 04-18-2013 |
20130130478 | Non-Volatile Memory Device And Method Of Manufacturing The Same - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 05-23-2013 |
20130270624 | GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE - A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced. | 10-17-2013 |
20130334593 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 12-19-2013 |
20140085961 | SEMICONDUCTOR MEMORY DEVICE - According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines. | 03-27-2014 |
20140094012 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate. | 04-03-2014 |
20140097484 | VERTICAL TYPE MEMORY DEVICE - A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections. | 04-10-2014 |
20140145255 | NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND CHANNELS AND METHODS OF FORMING THE SAME - A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device. | 05-29-2014 |
20140159137 | GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE - A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced. | 06-12-2014 |
20140175535 | MEMORY DEVICES CAPABLE OF REDUCING LATERAL MOVEMENT OF CHARGES - Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell. | 06-26-2014 |
20140187029 | VERTICAL TYPE MEMORY DEVICE - A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction. | 07-03-2014 |
20140193966 | METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves. | 07-10-2014 |
20140197471 | NON-VOLATILE MEMORY DEVICES HAVING REDUCED SUSCEPTIBILITY TO LEAKAGE OF STORED CHARGES AND METHODS OF FORMING SAME - Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. | 07-17-2014 |
20140231899 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 08-21-2014 |
20150054058 | MEMORY DEVICE - Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections. | 02-26-2015 |
20150060992 | SEMICONDUCTOR DEVICE, SYSTEMS AND METHODS OF MANUFACTURE - A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed. | 03-05-2015 |