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Kwang-Nam
Kwang-Nam Choi, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110103710 | APPARATUS AND METHOD OF REDUCING NOISE IN RANGE IMAGES - An apparatus and method of reducing noise in range images, the apparatus including: a maximum likelihood detection unit calculating an equation of observation points disposed in a plurality of grids that constitute range images representing three-dimensional (3D) coordinate information, to satisfy maximum log-likelihood on each coordinate axis in a coordinate space represented by the range images based on probability distribution of coordinate values assigned to each of the observation points and neighboring observation points; a linearization unit transforming equations calculated on each of the observation points into a linear equation that is a linear system on each coordinate axis in a coordinate space; a constraint detection unit calculating a constraint equation in which a unit tangent vector of each observation point and a unit tangent vector of a neighboring point are identical with each other on each coordinate axis of the range images; and a noise reduction unit reducing noise in range images by applying a resultant value that is obtained by calculating a value of a linear equation represented in the form of least squares together with the constraint equation by using a normal equation on a position of each observation point in the range images. Noise in range images in which noise is not uniformly distributed, may be well reduced so that a smooth curved surface having stable curvature may be obtained. | 05-05-2011 |
Kwang-Nam Kim, Yongin-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20100001287 | Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same - A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes. | 01-07-2010 |
| 20100245269 | Organic light emitting display apparatus and method of manufacturing the same - An organic light emitting display apparatus includes a substrate; a display unit formed on the substrate and comprising an organic light emitting device; and a touch panel formed on the display unit, wherein the touch panel further includes a sealing substrate, a ground layer formed on a surface of the sealing substrate, a first pattern layer formed on a surface of the sealing substrate opposite to the surface of the sealing substrate on which the ground layer is formed, a first insulating layer formed on the first pattern layer, a second pattern layer formed on the first insulating layer, and a second insulating layer formed on the second pattern layer. | 09-30-2010 |
Kwang-Nam Kim, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090286360 | Etchant and method for fabricating electric device including thin film transistor using the same - The present embodiments relate to an etchant and a method of fabricating an electric device including a thin film transistor. The etchant includes a fluorine ion (F | 11-19-2009 |
Kwang-Nam Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090058280 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus including: a substrate having a display area; a thin film transistor (TFT) disposed in the display area of the substrate; an electrode power supply line disposed outside the display area of the substrate; a first insulating layer covering the TFT and having a first open portion through which a portion or a whole top surface of the electrode power supply line is exposed; and a second insulating layer disposed on the first insulating layer and having a second open portion through which the first open portion of the first insulating layer is exposed, so that the second insulating layer does not contact the electrode power supply line. | 03-05-2009 |