| Patent application number | Description | Published |
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| 20080225623 | MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS - A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode. | 09-18-2008 |
| 20080278193 | Reference voltage generators for reducing and/or eliminating termination mismatch - A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator. | 11-13-2008 |
| 20080291753 | Semiconductor memory device and latency signal generating method thereof - A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal. | 11-27-2008 |
| 20080307285 | MEMORY DEVICES AND SYSTEMS INCLUDING ERROR-CORRECTION CODING AND METHODS FOR ERROR-CORRECTION CODING - In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer. | 12-11-2008 |
| 20090102523 | LINEAR DIGITAL PHASE INTERPOLATOR AND SEMI-DIGITAL DELAY LOCKED LOOP (DLL) - Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL. | 04-23-2009 |
| 20090251181 | Method and apparatus for tuning phase of clock signal - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 10-08-2009 |
| 20090267813 | Semiconductor devices, a system including semiconductor devices and methods thereof - Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced. | 10-29-2009 |
| 20090268528 | Semiconductor memory device and access method thereof - Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time. | 10-29-2009 |
| 20100026353 | Semiconductor device for constantly maintaining data access time - The semiconductor device may include a calibration circuit, a control unit, and a delay unit. The calibration circuit may be configured to output an output signal. The control unit may be configured to generate and output the control signal in response to the output signal of the calibration circuit. The control unit may generate the control signal by using a correlation between a signal transmission speed of the semiconductor device and the output signal of the calibration circuit. The delay unit may be configured to delay a clock signal in response to the control signal and output the delayed clock signal to the output driver. | 02-04-2010 |
| 20100091601 | CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT - A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device. | 04-15-2010 |
| 20100189160 | TEMPERATURE SENSING CIRCUIT OF SEMICONDUCTOR DEVICE - A temperature sensing circuit of a semiconductor device includes a code signal generator, a comparator, a reference clock generator and a final temperature code signal generator. The code signal generator is configured to output a first count signal having an increase rate that varies according to a change in temperature. The comparator is configured to receive the first count signal and a control signal, compare the first count signal with the control signal and output a comparison signal. The reference clock generator is configured to generate a reference clock having a uniform period regardless of the change in temperature during an activation period of the comparison signal. The final temperature code signal generator is configured to count pulses of the reference clock, generate a second count signal, modify the second count signal using an offset value, and output the modified second count signal as a final temperature code signal. | 07-29-2010 |
| 20100237902 | SEMICONDUCTOR DEVICE CAPABLE OF TESTING A TRANSMISSION LINE FOR AN IMPEDANCE CALIBRATION CODE - A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode. | 09-23-2010 |
| 20100259310 | DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER - A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal. | 10-14-2010 |
| 20100329041 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT - A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array. | 12-30-2010 |
| 20100329049 | SEMICONDUCTOR MEMORY DEVICE HAVING A LATENCY CONTROLLER - A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register. | 12-30-2010 |
| 20110001562 | HIGH SPEED LINEAR DIFFERENTIAL AMPLIFIER - A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier. | 01-06-2011 |
| 20110001569 | OSCILLATION CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - An oscillation circuit and a semiconductor device incorporating same are provided. The oscillation circuit includes an oscillation unit including a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases, when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters, when the control signal is deactivated, and a control unit configured to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node among the plurality of inverters and clock signals of which the phases lead that of a clock signal of the first node, when the oscillation enable signal is deactivated. | 01-06-2011 |
| 20110030064 | DATA MASK SYSTEM AND DATA MASK METHOD - A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information. | 02-03-2011 |
| 20110044123 | CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT - A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device. | 02-24-2011 |
| 20110128170 | Semiconductor devices, a system including semiconductor devices and methods thereof - Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced. | 06-02-2011 |
| 20110158030 | METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 06-30-2011 |
