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Kwang-Il
Kwang Il Jeong, Gumi-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110212662 | LAYOUT OF LIQUID CRYSTAL DISPLAY PANELS AND SIZE OF MOTHER SUBSTRATE - A layout of LCD panels and a size of the mother substrate are disclosed, to improve the efficiency in arrangement of the LCD panels, and to maximize the substrate efficiency, the layout comprising a mother substrate; a dummy region of 15 mm or less in a periphery of the mother substrate; and six LCD panels of the 26-inch model in a matrix of 2×3 on the mother substrate excluding the dummy region with a margin corresponding to 2˜4% of a length of the LCD panel. | 09-01-2011 |
Kwang Il Kim, Anyang-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090186613 | Method of performing random access procedure in wireless communication system - A method includes transmitting a random access preamble, receiving a random access response as a response of the random access preamble, wherein the random access response comprises an uplink resource assignment and a request for transmission of a Channel Quality Indicator (CQI), and transmitting the CQI in the uplink resource assignment. | 07-23-2009 |
Kwang Il Kim, Kimhae-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20090071301 | Automatic Lathe - The present relates to an automatic lathe, and more particularly, to an automatic lathe capable of mounting various tools with arranging a tool turret ( | 03-19-2009 |
Kwang Il Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100166879 | CANCELLOUS BONE GRAFT SUBSTITUTE AND METHOD OF MANUFACTURING THE SAME - A cancellous bone graft substitute and a method of manufacturing the cancellous bone graft substitute are provided, and more particularly, a cancellous bone graft substitute and a method of manufacturing the cancellous bone graft substitute by which defatting, demineralizing, cleaning, and sterilizing processes are performed within a short time using a supersonic cabitation without damaging a surface and an inside of a bone tissue so as to further rapidly, effectively supply an allogeneic or xenogeneic bone graft substitute. Internal and external concentrations of Ca++ of the allogeneic or xenogeneic bone graft substitute are effectively removed so as to maintain physical properties of the allogenetic or xenogeneic bone graft substitute. | 07-01-2010 |
Kwang-Il Choi, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100084473 | Radio Frequency Identification Tag for the Metal Product with High Thermal Resistance and the Fabricating Method Thereof - The present invention relates to a radio frequency identification tag having high thermal resistance for metal products and method of manufacturing thereof. The radio frequency identification tag according to the present invention comprises a printed circuit board made of epoxy glass; an antenna pattern and a transponder chip disposed on the upper surface of the printed circuit board; a first thermal resistant ink layer coated on the antenna pattern on the printed circuit board; a metal shielding layer attached to a lower surface of the printed circuit board; a second thermal resistant ink layer coated on the lower surface of the metal shielding layer; and an adhesive layer applied to the second thermal resistant ink layer, wherein a transponder chip protection layer made of thermal resistant is formed on the transponder chip. The radio frequency identification tag according to the present invention, has the advantages of preventing damage to a transponder chip and an antenna pattern even at high temperature environment, being capable of rapidly dissipating heat accumulated in the transponder chip, and being capable of remarkably reducing the likelihood of a transponder chip or an antenna pattern being damaged during the manufacturing process. | 04-08-2010 |
Kwang-Il Jung, Hwasung-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20100065896 | Image sensor including a pixel cell having an epitaxial layer, system having the same, and method of forming a pixel cell - A pixel cell includes a substrate, an epitaxial layer, and a photo converting device in the epitaxial layer. The epitaxial layer has a doping concentration profile of embossing shape, and includes a plurality of layers that are stacked on the substrate. The photo converting device does not include a neutral region that has a constant potential in the vertical direction. Therefore, the image sensor including the pixel cell has high quantization efficiency, and a crosstalk between photo-converting devices is decreased. | 03-18-2010 |
Kwang-Il Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100178138 | APPARATUS AND METHOD FOR LOADING CARTRIDGE HOLDING REACTANT INTO REACTANT CHAMBER OF REACTOR - An apparatus for loading cartridges holding reactants into reactant chambers of a reactor is provided. The apparatus includes: at least one guide rail which transfers a cartridge; an extraction unit comprising at least one storage portion and a blocking portion, the extraction unit moving between a first position in which the blocking portion blocks an outlet of the guide rail and a second position in which the cartridge is output through the outlet of the guide rail and stored by the storage portion; a transfer unit which moves the reactor so that a chamber of the reactor is aligned with the storage portion; and an insertion unit which moves the cartridge from the storage portion into the chamber of the reactor. | 07-15-2010 |
Kwang-Il Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100167672 | MOBILE TERMINAL HAVING MULTIPLE ANTENNAS AND ANTENNA INFORMATION DISPLAY METHOD THEREOF - A mobile terminal having multiple antennas and an antenna information display method of the mobile terminal are disclosed. Downlink signals are received through the multiple antennas, a channel state of each antenna is measured, and whether or not each antenna needs to be adjusted or an actual channel measurement value are displayed based on the measured channel state information and an antenna setting mode. Thus, a user can check an antenna with a poor reception performance by using the antenna adjustment information or the actual channel measurement value for antenna adjustment, and easily adjust the direction of the antennas. | 07-01-2010 |
Kwang-Il Lee, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20110080914 | ETHERNET TO SERIAL GATEWAY APPARATUS AND METHOD THEREOF - Provided is an Ethernet-to-serial gateway apparatus including: a buffer manager to verify a characteristic of a data packet received via an Ethernet interface, and to thereby select a buffer for storing the data packet, and to store the data packet in the selected buffer; a packet scheduler to extract a data packet from the buffer according to a predetermined policy; a packet distributor to verify a destination address of the extracted data packet, and to thereby obtain serial interface information associated with at least one target apparatus to which the extracted data packet is transmitted; and a serial communication unit to transmit the extracted data packet to the at least one target apparatus via a corresponding serial interface based on the serial interface information. | 04-07-2011 |
Kwang-Il Oh, Daejeon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110285679 | CHIP-ON-GLASS TYPE LIQUID CRYSTAL DISPLAY DEVICE - A chip-on-glass (COG) type liquid crystal display device minimizes a reflected wave from an input terminal of a source driver IC, regardless of the resistance value of a transmission line on a glass substrate, through the use of impedance matching at a front terminal of an LOG and impedance matching at an output terminal of a timing controller, thereby enhancing the frequency characteristic while maintaining a slim and lightweight design, so that it is possible to express a high-resolution high-quality image. | 11-24-2011 |
Kwang-Il Park, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080225626 | CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE - Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal. | 09-18-2008 |
| 20090271652 | METHODS AND COMPUTER PROGRAM PRODUCTS FOR DETERMINING SIMULTANEOUS SWITCHING INDUCED DATA OUTPUT TIMING SKEW - A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device. | 10-29-2009 |
| 20100091600 | CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE - Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal. | 04-15-2010 |
Kwang-Il Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100045491 | INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA - An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data. | 02-25-2010 |
| 20100220485 | SIDE ILLUMINATION LENS AND LUMINESCENT DEVICE USING THE SAME - The present invention relates to a side illumination lens and a luminescent device using the same, and provides a body, a total reflection surface with a total reflection slope with respect to a central axis of the body, and a linear and/or curved refractive surface(s) formed to extend from a periphery of the total reflection surface; and a luminescent device including the lens. According to the present invention, a lens with total internal reflection surfaces with different slopes, and a linear and/or curved refractive surface(s) allows light emitted forward from a luminescent chip to be guided to a side of the lens. Further, a linear surface(s) formed in a direction perpendicular or parallel to a central axis of a lens and a curved surface are formed on an edge of the lens so that a process of fabricating the lens is facilitated, thereby reducing a defective rate and fabrication costs of the lens. | 09-02-2010 |
| 20110254045 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE SYSTEM HAVING AT LEAST TWO HEAT SINKS - There is provided a light emitting diode package having at least two heat sinks. The light emitting diode package includes a main body, at least two lead terminals fixed to the main body, and at least two heat sinks of electrically and thermally conductive materials, the heat sinks being fixed to the main body. The at least two heat sinks are separated from each other. Thus, high luminous power can be obtained mounting a plurality of light emitting diode dies in one LED package. Further, it is possible to embody polychromatic lights mounting LED dies emitting different wavelengths of light each other in the LED package. | 10-20-2011 |
Kwang-Il Park US
| Patent application number | Description | Published |
|---|---|---|
| 20110029697 | MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS - A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode. | 02-03-2011 |
| 20110185219 | MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS - A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode. | 07-28-2011 |