| Patent application number | Description | Published |
|---|
| 20090122593 | Write driver circuit for phase-change memory, memory including the same, and associated methods - A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit. | 05-14-2009 |
| 20090122601 | POWER SUPPLYING CIRCUIT AND PHASE-CHANGE RANDOM ACCESS MEMORY INCLUDING THE SAME - Embodiments of the invention provide a power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks. | 05-14-2009 |
| 20090168494 | Semiconductor device having resistance based memory array, method of operation, and systems associated therewith - In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array. | 07-02-2009 |
| 20090251953 | Variable resistance memory device - A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines. | 10-08-2009 |
| 20090251954 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit. | 10-08-2009 |
| 20100124101 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE - Provided is a phase-change random access memory device. The phase-change random access memory device includes a phase-change memory cell array having multiple phase-change memory cells, a sensing unit and a discharge unit. The sensing unit detects data, stored in a phase-change memory cell to be sensed of the multiple phase-change memory cells, during a sensing period. The discharge unit discharges at least one node of multiple nodes positioned on a sensing path between the phase-change memory cell array and the sensing unit during a period other than the sensing period. | 05-20-2010 |
| 20100124103 | Resistance-change random access memory device - A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations. | 05-20-2010 |
| 20100124105 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit. | 05-20-2010 |
| 20100125716 | RESISTANCE VARIABLE MEMORY DEVICE - A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received | 05-20-2010 |
| 20100268872 | DATA STORAGE SYSTEM COMPRISING MEMORY CONTROLLER AND NONVOLATILE MEMORY - A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state. | 10-21-2010 |
