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Kwan Weon Kim
Kwan Weon Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080225497 | Semiconductor integrated circuit and semiconductor package module having the same - A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively. | 09-18-2008 |
| 20100283519 | CLOCK SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit. | 11-11-2010 |
| 20100290302 | FUSE CIRCUIT AND DRIVING METHOD THEREOF - A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node. | 11-18-2010 |
| 20110058432 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is provided that includes a first pad, a data storage and input/output block configured to store and output data by using a data strobe signal and a clock signal inputted through the first pad, and a timing compensation unit configured to delay the clock signal to generate the data strobe signal. | 03-10-2011 |
Kwan Weon Kim, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100157696 | SEMICONDUCTOR MEMORY APPARATUS AND A METHOD FOR READING DATA STORED THEREIN - A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of data, and further configured to generate a plurality of inversion data based on the decision; and a data output section configured to receive the plurality of inversion data, invert or output, without an inversion the plurality of inversion data in response to a mode signal, and generate a plurality of output data. | 06-24-2010 |
Kwan Weon Kim, Ichon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090058458 | DIGITAL-TO-ANALOG CONVERTING CIRCUIT AND APPARATUS FOR ON-DIE TERMINATION USING THE SAME - A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code. | 03-05-2009 |
| 20090121786 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit. | 05-14-2009 |
Kwan Weon Kim, Kyungki-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090010082 | DATA TRANSFER APPARATUS IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A data transfer apparatus in a semiconductor memory device includes a DQ pad, a DQS pad, a DQ driver for transferring the data signal to the DQ pad according to a driver select signal, and a DQS driver for transferring data strobe signal to the DQS pad according to the driver select signal. Any one of the DQ driver and the DQS driver is activated by the driver select signal, and the driver select signal is generated by one of EMRS control code, MRS control code and test mode code. | 01-08-2009 |
Kwan Weon Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120007631 | INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING DATA OUTPUT IMPEDANCE - An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal. | 01-12-2012 |