Patent application number | Description | Published |
20090157986 | MEMORY CONTROLLER - A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal. | 06-18-2009 |
20100070821 | METHOD AND APPARATUS FOR DETECTING FREE PAGE AND A METHOD AND APPARATUS FOR DECODING ERROR CORRECTION CODE USING THE METHOD AND APPARATUS FOR DETECTING FREE PAGE - A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value. | 03-18-2010 |
20130061113 | METHOD OF CORRECTING ERRORS AND MEMORY DEVICE USING THE SAME - A method of correcting errors includes receiving a codeword including main data and parity data stored in a memory cell array to perform an error check and correction (ECC) decoding on the codeword and selectively performing an error correction on the codeword based on a result of the ECC decoding using asymmetry of error occurrence of the main data. | 03-07-2013 |
20130219208 | METHOD OF CORRECTING A DUTY RATIO OF A DATA STROBE SIGNAL - A method of correcting a duty ratio of a data strobe signal is provided. By the method, a duty ratio of a data strobe signal output from a semiconductor memory device is detected and a duty ratio of a clock signal input to the semiconductor memory device is adjusted based on the duty ratio of the data strobe signal. | 08-22-2013 |
20130219246 | Method and Apparatus for Detecting Free Page and a Method and Apparatus for Decoding Error Correction Code Using the Method and Apparatus for Detecting Free Page - A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value. | 08-22-2013 |
20140082269 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST CONTROLLING SAME, AND METHOD OF OPERATING eMMC SYSTEM - A method of operating an eMMC system includes a host sending SEND_EXT_CSD command to obtain busy control clock information from an eMMC. The busy control clock information is then used to control provision of a host-provided clock to the eMMC while the eMMC is in a busy state. | 03-20-2014 |
20140115656 | SECURITY MANAGEMENT UNIT, HOST CONTROLLER INTERFACE INCLUDING SAME, METHOD OPERATING HOST CONTROLLER INTERFACE, AND DEVICES INCLUDING HOST CONTROLLER INTERFACE - A method of operating a host controller interface includes receiving a buffer descriptor including sector information from a main memory, fetching data by using a source address included in the buffer descriptor, selecting one of a plurality of entries included in a security policy table by using the sector information, and determining whether to encrypt the fetched data by using a security policy included in the selected entry. | 04-24-2014 |
20140195742 | SYSTEM ON CHIP INCLUDING MEMORY MANAGEMENT UNIT AND MEMORY ADDRESS TRANSLATION METHOD THEREOF - A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets. | 07-10-2014 |
20140244908 | INTEGRATED CIRCUIT FOR COMPUTING TARGET ENTRY ADDRESS OF BUFFER DESCRIPTOR BASED ON DATA BLOCK OFFSET, METHOD OF OPERATING SAME, AND SYSTEM INCLUDING SAME - A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device. | 08-28-2014 |
20140258674 | SYSTEM-ON-CHIP AND METHOD OF OPERATING THE SAME - A system on chip (SoC) includes a central processing unit (CPU), an intellectual property (IP) block, and a memory management unit (MMU). The CPU is configured to set a prefetch direction corresponding to a working set of data. The IP block is configured to process the working set of data. The MMU is configured to prefetch a next page table entry from a page table based on the prefetch direction during address translation between a virtual address of the working set of data and a physical address. | 09-11-2014 |