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Kwack, KR
Heeyoung Kwack, Paju-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120104404 | HIGH LIGHT TRANSMITTANCE IN-PLANE SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a high light transmittance in-plan switching liquid crystal display device and a method for manufacturing the same. The liquid crystal display device includes: a substrate; a gate line disposed in horizontal direction on the substrate; a gate insulating layer covering the gate line; a data line disposed in vertical direction on the gate insulating layer; an additional insulating layer on the data line having same size and shape with the data line; a passivation layer covering the additional insulating layer; and a common electrode overlapping with the data line on the passivation layer. According to the present disclosure, the failure due to the parasitic capacitance and the load for driving the display panel are reduced and it is possible to make large and high definition display panel. | 05-03-2012 |
Hee Young Kwack, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110156040 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A thin film transistor array substrate including a substrate, a gate line intersecting a data line to define a pixel region on the substrate, a switching element disposed at an intersection of the gate line and the data line, a plurality of pixel electrodes and a plurality of first common electrodes alternately arranged in the pixel region, a second common electrode overlapping the data line and interposed between a gate insulation film and a protective film, a first storage electrode on the substrate, a second storage electrode overlapping the first storage electrode, and an organic insulation film on the switching element, the second storage electrode, the data line, a gate pad, and a data pad, wherein the second common electrode covers the data line, the protective film, the organic insulation film, and the gate insulation film, and has inclined surfaces connected to the surface of the substrate. | 06-30-2011 |
Ho Sang Kwack, Chungcheongnam-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090296766 | QUANTUM DOT LASER DIODE AND METHOD OF MANUFACTURING THE SAME - Provided are a quantum dot laser diode and a method of manufacturing the same. The method of manufacturing a quantum dot laser diode includes the steps of: forming a grating structure layer including a plurality of gratings on a substrate; forming a first lattice-matched layer on the grating structure layer; forming at least one quantum dot layer having at least one quantum dot on the first lattice-matched layer; forming a second lattice-matched layer on the quantum dot layer; forming a cladding layer on the second lattice-matched layer; and forming an ohmic contact layer on the cladding layer. Consequently, it is possible to obtain high gain at a desired wavelength without affecting the uniformity of quantum dots, so that the characteristics of a laser diode can be improved. | 12-03-2009 |
| 20110165716 | QUANTUM DOT LASER DIODE AND METHOD OF FABRICATING THE SAME - A quantum dot laser diode and a method of fabricating the same are provided. The quantum dot laser diode includes: a first clad layer formed on an InP substrate; a first lattice-matched layer formed on the first clad layer; an active layer formed on the first lattice-matched layer, and including at least one quantum dot layer formed of an InAlAs quantum dot or an InGaPAs quantum dot which is grown by an alternate growth method; a second lattice-matched layer formed on the active layer; a second clad layer formed on the second lattice-matched layer; and an ohmic contact layer formed on the second clad layer. | 07-07-2011 |
Ho Sang Kwack, Cheonan-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100260223 | Quantum dot laser diode and method of fabricating the same - A quantum dot laser diode and a method of fabricating the same are provided. The quantum dot laser diode includes: a first clad layer formed on an InP substrate; a first lattice-matched layer formed on the first clad layer; an active layer formed on the first lattice-matched layer, and including at least one quantum dot layer formed of an InAlAs quantum dot or an InGaPAs quantum dot which is grown by an alternate growth method; a second lattice-matched layer formed on the active layer; a second clad layer formed on the second lattice-matched layer, and an ohmic contact layer formed on the second clad layer. | 10-14-2010 |
Hyun-Sun Kwack, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110223915 | APPARATUS AND METHOD FOR ALLOWING FEMTO BASE STATION TO EFFICIENTLY PERFORM BEACONING IN WIRELESS COMMUNICATION SYSTEM - An apparatus and a method for allowing a femto base station to efficiently perform beaconing in a wireless communication system are provided. The method includes obtaining a System Information Block (SIB) message of a neighbor macro base station transmitted to a terminal by the neighbor macro base station. Information of the femto base station is added to the obtained SIB message of the macro base station and the SIB message is updated. The updated SIB message is transmitted to the terminal. | 09-15-2011 |
Il Young Kwack, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110250315 | METHOD FOR PREPARING FERMENTED TEA USING BACILLUS SP. STRAINS (As Amended) - Disclosed is a method for manufacturing fermented tea having superior flavor using | 10-13-2011 |
Kae Dal Kwack, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110075503 | MAIN DECODING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal. | 03-31-2011 |
| 20110085393 | SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF - A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line. | 04-14-2011 |
Kae-Dal Kwack, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090108327 | Gate pattern having two control gates, flash memory including the gate pattern and methods of manufacturing and operating the same - Provided may be a gate pattern, flash memory and methods of manufacturing and operating the same. A gate pattern may include a floating gate on a tunneling dielectric layer, an inter-gate dielectric layer on the floating gate, a first control gate on the inter-gate dielectric layer, and a second control gate on the inter-gate dielectric layer and spaced apart from the first control gate. Each of the control gates sets four states according to an application time of a program voltage applied to the control gates. Thus, one control gate may program 2-bit data. | 04-30-2009 |
| 20090206385 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate. | 08-20-2009 |
| 20110069555 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate. | 03-24-2011 |
| 20110216595 | NAND FLASH MEMORY OF USING COMMON P-WELL AND METHOD OF OPERATING THE SAME - A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection. | 09-08-2011 |
Kyoung Kuk Kwack, Suwon KR
| Patent application number | Description | Published |
|---|---|---|
| 20100015898 | Conditioner for Chemical Mechanical Planarization Pad - The present invention provides a conditioner for CMP pad required for global planarization of wafer to achieve high integration of a semiconductor element. The conditioner for CMP pad includes a metal substrate having abrasive particles fixed thereto, a plurality of abrasive particles fixed to the metal substrate, and a layer of metal binder fixing the abrasive particles to the metal substrate. The abrasive particles include at least one pattern. The pattern includes at least one row of abrasive particles and the abrasive particles include bigger abrasive particles and smaller abrasive particles. In addition, a diameter difference between smaller and bigger abrasive particles is 10 to 40%. The present invention ensures uniform dressing of conditioner, superior dressing efficiency and superior performance reproducibility. | 01-21-2010 |
Kyu-Bum Kwack, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080317879 | Herb Composition for Asthma Maintenance Therapy and Manufacturing Method Thereof - The present invention relates to a herb composition for asthma maintenance therapy based on Chungsangboha-tang, which is known to be effective in asthma, capable of reducing the long-term suffering of asthma patients and improving their quality of lives and a manufacturing method thereof. The herbal composition of the present invention is characterized by comprising 5-18 parts by weight of | 12-25-2008 |
Seo Shin Kwack, Gwacheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110111784 | METHOD OF ALLOCATING UPLINK RESOURCES IN WIRELESS COMMUNICATION SYSTEM - A method of allocating uplink resources in a wireless communication system is provided. The method comprises generating a first message which has a preamble and adaptively further includes resource request information based on a communication state with a base station and transmitting the first message to the base station. | 05-12-2011 |
Seung Wook Kwack, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120120743 | SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes a shared pad which is configured to output a read operation control signal in a read operation and receive a write operation control signal in a write operation. | 05-17-2012 |
Seung Wook Kwack, Daejeon-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090010082 | DATA TRANSFER APPARATUS IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A data transfer apparatus in a semiconductor memory device includes a DQ pad, a DQS pad, a DQ driver for transferring the data signal to the DQ pad according to a driver select signal, and a DQS driver for transferring data strobe signal to the DQS pad according to the driver select signal. Any one of the DQ driver and the DQS driver is activated by the driver select signal, and the driver select signal is generated by one of EMRS control code, MRS control code and test mode code. | 01-08-2009 |
Seung Wook Kwack, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110026337 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A circuit includes a data input/output unit configured to connect to a first memory bank and a second memory bank. The data input/output unit includes a data switching unit configured to be selectively coupled with the first or second memory bank in response to a bank selection signal, and an input/output driver configured to amplify an output of the data switching unit and transfer the amplified output to a global data line during the read operation, and configured to amplify data from the global data line and transfer the amplified data to the data switching unit during the write operation. | 02-03-2011 |
| 20110075503 | MAIN DECODING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal. | 03-31-2011 |
| 20110085393 | SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF - A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line. | 04-14-2011 |
Seung-Wook Kwack, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090022005 | APPARATUS AND METHOD OF CONTROLLING BANK OF SEMICONDUCTOR MEMORY - An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption. | 01-22-2009 |