Kusuda
Charles E. Kusuda, Mukiltco, WA US
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20120156979 | METHOD AND APPARATUS FOR AIR FLOW CONTROL IN AN AIRCRAFT SIDEWALL VOLUME - An aircraft fuselage sidewall may include an aircraft sidewall volume and a flow controller. The aircraft sidewall volume may be delineated by an aircraft skin forming an outboard boundary of the aircraft sidewall volume, a passenger cabin sidewall forming an inboard boundary of the aircraft sidewall volume and fuselage frame structures forming axial boundaries of the aircraft sidewall volume. The flow controller may be positioned at a portion of the aircraft sidewall volume to selectably control air flow through the aircraft sidewall volume. | 06-21-2012 |
Charles E. Kusuda, Mukilteo, WA US
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20140251585 | Micro-lattice Cross-flow Heat Exchangers for Aircraft - An aircraft micro-lattice cross-flow heat exchanger and methods are presented. A first aircraft fluid source inlet provides a first fluid from a first aircraft system, and a second aircraft fluid source inlet provides a second fluid from a second aircraft system. A structural body supports aviation induced structural loads and exchanges heat between the first fluid and the second fluid. The structural body comprises hollow channels forming two interpenetrating fluidically isolated volumes that flow the first fluid within the hollow channels and flow the second fluid external to the hollow channels isolated from the first fluid. The hollow channels comprise a hollow three-dimensional micro-truss comprising hollow truss elements extending along at least three directions, and hollow nodes interpenetrated by the hollow truss elements. | 09-11-2014 |
Yoshinori Kusuda, Woburn, MA US
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20100060352 | Auto-correction feedback loop for offset and ripple suppression in a chopper-stabilized amplifier - A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output. | 03-11-2010 |
20110043251 | Opportunistic Timing Control in Mixed-Signal System-On-Chip Designs - An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive. | 02-24-2011 |
Yoshinori Kusuda, Malden, MA US
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20110043270 | LOW POWER AND LOW NOISE SWITCHED CAPACITOR INTEGRATOR WITH FLEXIBLE INPUT COMMON MODE RANGE - An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects. | 02-24-2011 |
Yoshinori Kusuda, Woburn State, MA US
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20110038083 | GUARDED ELECTRICAL OVERSTRESS PROTECTION CIRCUIT - Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node. | 02-17-2011 |
Yoshinori Kusuda, San Jose, CA US
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20130015322 | APPARATUS AND METHOD FOR REDUCING COMMON-MODE ERRORAANM KUSUDA; YoshinoriAACI San JoseAAST CAAACO USAAGP KUSUDA; Yoshinori San Jose CA USAANM CARREAU; Gary RobertAACI PlaistowAAST NHAACO USAAGP CARREAU; Gary Robert Plaistow NH USAANM COLN; Michael C.AACI LexingtonAAST MAAACO USAAGP COLN; Michael C. Lexington MA US - Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels. | 01-17-2013 |
20130194118 | CORRELATED DOUBLE-SAMPLE DIFFERENCING WITHIN AN ADC - A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage. | 08-01-2013 |
20130207727 | APPARATUS AND METHODS FOR REDUCING OUTPUT NOISE OF A SIGNAL CHANNEL - Apparatus and methods for reducing output noise of a signal channel are provided. In one embodiment, a signal channel includes an amplifier for amplifying an input signal to generate an amplified signal. The amplifier includes a bias circuit that controls a bias current of the amplifier based on a voltage across a biasing capacitor. The apparatus further includes a sampling circuit for sampling the amplified signal. The sampling circuit generates an output signal based on a difference between a first sample of the amplified signal taken at a first time instance and a second sample of the amplified signal taken at a second time instance. The bias circuit samples a bias voltage onto the biasing capacitor before the first time instance and holds the voltage across the biasing capacitor substantially constant between the first time instance and the second time instance to reduce noise of the output signal. | 08-15-2013 |
20140193090 | APPARATUS AND METHODS FOR REDUCING COMMON-MODE NOISE IN AN IMAGING SYSTEM - Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels. | 07-10-2014 |