Patent application number | Description | Published |
20110116730 | ZIPPERED POUCH WITH SPOUT - A pouch comprises a plurality of plastic sheets sealed on periphery, has a contents spout and a plastic zipper arranged in a fused state between the sheets whose outer periphery is sealed, and is heat-sterilized after being filled with contents. A a barrier portion is formed in a portion of the pouch interior set further toward the contents and away from the plastic zipper, the barrier portion formed in a state in which a film base material has been folded over. As a result, even if any damage is imparted during the step for manufacturing the plastic zipper or the step for mounting the zipper in the pouch, there will be no incidence of the contents leaking from the barrier portion and reaching the zipper portion due to heat and pressure encountered when retort sterilization, boiling, or another type of heat sterilization is performed after the pouch has been filled with foodstuffs or other material. | 05-19-2011 |
20120263400 | PLASTIC POUCH AND MANUFACTURING METHOD THEREFOR - At least one of an obverse surface film and reverse surface film, which are used to together constitute a plastic pouch, is folded back across the entire width of the plastic pouch, and peripheral edge portions of the pouch are heat-sealed, to thereby form, on at least one position, a folded-back section communicating with the body of the pouch. | 10-18-2012 |
Patent application number | Description | Published |
20130193899 | MOTOR DRIVE CONTROL DEVICE AND OPERATING METHOD THEREOF - The present invention properly starts up various types of motors under operating conditions where motor operations are performed in a wide range of temperature and power supply voltage. Output drive controllers supply PWM drive output signals to the output pre-driver in such a manner as to minimize the error between a current instruction signal and a current detection digital signal. In response to a detected induced voltage generated from a voltage detector upon startup of a motor, an initial acceleration controller supplies initial acceleration output signals specifying a conducting phase for initial acceleration of the motor to the output drive controllers. The initial acceleration controller, the output drive controllers, and an output driver make a conducting phase change and perform a PWM drive to provide the initial acceleration of the motor in response to the detected induced voltage and to an error upon startup of the motor. Upper-limit duty values for the PWM drive output signals to be supplied from the output drive controllers to the output pre-driver during the period of the initial acceleration can be arbitrarily set in the output drive controllers. | 08-01-2013 |
20140021886 | MOTOR DRIVE CONTROL DEVICE AND OPERATION METHOD THEREOF - When a motor drive control device is integrated in a semiconductor integrated circuit having a small chip area, calibration for improving the accuracy of detection of a counter electromotive voltage, which is for detecting the speed of a motor, is enabled. A first multiplier performs multiplication between a drive current detection signal and first gain information in a first register. A subtractor performs subtraction between a drive voltage command signal and a first multiplication result in the first multiplier. A second multiplier performs multiplication between a subtraction result in the subtractor and second gain information in a second register to generate counter electromotive voltage information as information on a second multiplication result. The drive voltage command signal in a control unit is set to a predetermined value to generate a condition which maintains the speed of the motor and a counter electromotive voltage at substantially zero. | 01-23-2014 |
20140084889 | POWER SUPPLY DEVICE WITH SHARED INDUCTIVE ELEMENTS UNDER SWITCH CONTROL - A power supply device is responsive to load changes. The power supply device includes a switch control circuit, a charge control circuit, and a discharge control circuit. The switch control circuit controls switches so that electrical power is charged into an inductor, discharged from the inductor, and distributed to first and second capacitors in a time-division manner based on a switching cycle. The charge control circuit controls the amount of electrical power to be charged into the inductor based on a first amount of error between a first output power supply voltage and its target value and a second amount of error between a second output power supply voltage and its target value. The discharge control circuit controls a distribution ratio at which the electrical power discharged from the inductor is distributed to the first and second capacitors based on the ratio between the first and second amounts of error. | 03-27-2014 |
20140203751 | MOTOR DRIVE CONTROLLER AND METHOD FOR OPERATING THE SAME - A motor driver controller including a difference control section; a driver output section; a drive current detection amplifier; and a load short-circuit detection circuit. A motor and sensing resistor is coupled in series and coupled to an output terminal of the driver output section. The difference control section generates a drive voltage command signal in response to a drive current command value and a drive current detection signal. The driver output section drives the motor and sensing resistor, in response to the drive voltage command signal, and a drive current detection amplifier generates a signal fed to the difference control section, in response to a drive current of the sensing resistor. The load short-circuit detection circuit detects an abnormal oscillation waveform signal caused by a short-circuit state between the both ends of the motor. | 07-24-2014 |
20140333243 | MOTOR DRIVE CONTROL DEVICE AND OPERATING METHOD THEREOF - Motor Drive Control Device configured to properly start up various types of motors under operating conditions where motor operations are performed in a wide range of temperature and power supply voltage, includes output drive controllers that supply PWM drive output signals to an output pre-driver in such a manner as to minimize the error between a current instruction signal and a current detection digital signal. In response to a detected induced voltage generated from a voltage detector upon startup of a motor, an initial acceleration controller supplies initial acceleration output signals specifying a conducting phase for initial acceleration of the motor to the output drive controllers. The initial acceleration controller, the output drive controllers, and an output driver make a conducting phase change and perform a PWM drive to provide the initial acceleration of the motor. | 11-13-2014 |
20150123576 | MOTOR DRIVE CONTROL DEVICE AND OPERATION METHOD THEREOF - When a motor drive control device is integrated in a semiconductor integrated circuit having a small chip area, calibration for improving the accuracy of detection of a counter electromotive voltage, which is for detecting the speed of a motor, is enabled. A first multiplier performs multiplication between a drive current detection signal and first gain information in a first register. A subtractor performs subtraction between a drive voltage command signal and a first multiplication result in the first multiplier. A second multiplier performs multiplication between a subtraction result in the subtractor and second gain information in a second register to generate counter electromotive voltage information as information on a second multiplication result. The drive voltage command signal in a control unit is set to a predetermined value to generate a condition which maintains the speed of the motor and a counter electromotive voltage at substantially zero. | 05-07-2015 |
20150262599 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD FOR THE SAME - The present invention realizes a calibration operation for detecting a motor speed, without employing digital correcting by an external CPU. The calibration operation calculates a comparison reference value corresponding to aback EMF detection signal of a back EMF detector circuit when a zero current flows through a motor and when an arm is fixed. Accordingly, the back EMF detection signal of the back EMF detector circuit is set as the first value and the second value responding to the non-zero current flowing through the motor, and the semiconductor integrated circuit calculates the comparison reference value from the first value and the second value. The difference between the comparison reference value and the comparison input value as the back EMF detection signal of the back EMF detector circuit is reduced by adjusting the gain of an internal amplifier of the back EMF detector circuit by an adjustment unit. | 09-17-2015 |
Patent application number | Description | Published |
20090131291 | LUBRICATING OIL COMPOSITION - The present invention provides a lubricating oil composition which is less in evaporation loss even having a low viscosity and excellent in lubricating properties such as low-temperature viscosity characteristics and anti-seizure properties and in oxidation stability, suitable for use in engines, automatic transmissions, manual transmissions, final reduction gear units, and continuously variable transmissions. The lubricating oil composition comprises (A) a lubricating base oil and (B) a poly(meth)acrylate additive in such an amount that the kinematic viscosity at 100° C. of the composition (Vc) is from 3 to 15 mm | 05-21-2009 |
20100016195 | Lube Base Oil, Lubricating Oil Composition For Internal Combustion Engine, And Lubricating Oil Composition For Drive Transmissoin Device - The lubricating base oil of the invention satisfies at least one of conditions (a) or (b) below. The lubricating oil composition for an internal combustion engine according to the invention comprises the lubricating base oil of the invention, an ashless antioxidant containing essentially no sulfur as a constituent element, and at least one compound selected from among ashless antioxidants containing sulfur as a constituent element and organic molybdenum compounds. Also, a lubricating oil composition for a power train device according to the invention comprises the lubricating base oil of the invention, a poly(meth)acrylate-based viscosity index improver and a phosphorus-containing compound. | 01-21-2010 |
20100035777 | Lubricant base oil, lubricant composition for internal combustion engine and lubricant composition for driving force transmitting device - The lubricating base oil of the invention is characterized by satisfying at least one of the following conditions (a) or (b).
| 02-11-2010 |
20100041572 | Lube Base Oil, Process for Production Thereof, and Lubricating Oil Composition - The present invention provides a lubricating base oil comprising saturated components of 90% by mass or greater, wherein the proportion of cyclic saturated components among the saturated components is not greater than 40% by mass, and by having a viscosity index of 110 or higher and an iodine value of not greater than 2.5. The lubricating base oil of the invention exhibits excellent viscosity-temperature characteristics and heat and oxidation stability while also allowing additives to exhibit a higher level of function when additives are included. The lubricating base oil of the invention is suitable for use in various lubricating oil fields, and is especially useful for reducing energy loss and achieving energy savings in devices in which the lubricating base oil is applied. | 02-18-2010 |
Patent application number | Description | Published |
20110206627 | O/W Emulsified Composition - The present invention provides an O/W emulsified composition excellent in formulation stability, feeling in use, and UV protection ability. The emulsified composition according to the present invention is an O/W emulsified composition, wherein (i) a first oil phase and (ii) a second oil phase are dispersed separately in an aqueous phase,
| 08-25-2011 |
20110206628 | O/W Emulsified Composition - The present invention provides an O/W emulsified composition which contains an organic UV absorber in an oil state such as octocrylene and a solid organic UV absorber, and is excellent in UV protection ability, formulation stability, and feeling in use. The composition according to the present invention is an O/W emulsified composition, comprising: (a) an organic UV absorber in an oil state at 20° C., comprising (a1) octocrylene; (b) an organic UV absorber in a solid state at 20° C., selected from (b1) bis-ethylhexyloxyphenol methoxyphenyl triazine and (b2) methylene bis-benzotriazolyl tetramethylbutylphenol; and (c) a polyoxyethylene/polyoxyalkylene alkyl ether block polymer represented by formula (1) or (2): | 08-25-2011 |
20110236447 | Oil-In-Water Cosmetics - The present invention provides an oil-in-water cosmetic excellent in emulsion stability. The oil-in-water cosmetic includes (a) oil-droplet particles consisting of an oil component to be emulsified; (b) vesicle particles for stabilizing the oil-droplet particles; and (c) an aqueous phase containing water and a monohydric aliphatic alcohol having 1 to 4 carbon atoms. It is preferred that the vesicle particles are formed with an amphiphilic substance which spontaneously forms vesicle particles, and that they are localized on surfaces of the oil-droplet particles. It is preferred that the amphiphilic substance be a polyoxyethylene hydrogenated castor oil derivative represented by the following formula (1), wherein E=L+M+N+X+Y+Z, and that said E which represents the average addition mole number of ethylene oxide is 10 to 20. | 09-29-2011 |
Patent application number | Description | Published |
20100100684 | SET ASSOCIATIVE CACHE APPARATUS, SET ASSOCIATIVE CACHE METHOD AND PROCESSOR SYSTEM - A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address. | 04-22-2010 |
20100100685 | EFFECTIVE ADDRESS CACHE MEMORY, PROCESSOR AND EFFECTIVE ADDRESS CACHING METHOD - An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index. | 04-22-2010 |
20110231593 | VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR - An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. | 09-22-2011 |
20140164702 | VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR - An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. | 06-12-2014 |