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| 20110064432 | DEVELOPING DEVICE, PROCESS CARTRIDGE, AND IMAGE FORMING APPARATUS - A disclosed developing device includes a toner carrying member having electrodes, a toner supply unit supplying the toner to the toner carrying member, and a hopping electric field generator unit generating electric field to cause the toner hopping on the toner carrying member by applying a pulse voltage to the electrodes. The hopping electric field generator unit includes a pulse voltage generator circuit generating the pulse voltage, a first direct-current power source supplying bias to the pulse voltage generator circuit for regulating a peak value of the pulse voltage, and a second direct-current power source having a same polarity with a toner charging polarity, and outputting a variable voltage level. The hopping electric field generator unit controls the peak value of the pulse voltage by changing an output of the first power source and a mean thereof by changing an output of the second power source. | 03-17-2011 |
| 20110164892 | DEVELOPMENT DEVICE, PROCESS CARTRIDGE INCORPORATING SAME, AND IMAGE FORMING APPARATUS INCORPORATING SAME - A development device includes a developer container, a rotary developer carrier that is disposed facing the latent image carrier and including multiple outer electrodes arranged in a circumferential direction of the developer carrier, an inner electrode electrically insulated from the multiple outer electrodes, an insulation layer disposed between the inner and outer electrodes, and a surface layer overlaying the outer electrodes and electrically insulating the multiple outer electrodes from each other, a bias power source to generate electrical fields that change with time by applying a first and second bias voltages to the inner and outer electrodes, respectively, an electrical field adjuster to regulate the electrical fields in accordance with a thickness of the surface layer of the developer carrier, and a controller. | 07-07-2011 |
| 20110182626 | DEVELOPMENT DEVICE, PROCESS CARTRIDGE INCORPORATING SAME, AND IMAGE FORMING APPARATUS INCORPORATING SAME - A development device includes a toner carrier including first and second groups of electrodes, a toner supplier, and an electrical field generator to generate an electrical field for causing toner to hop along the surface of the toner carrier. The electrical field generator includes a positive-phase pulse voltage generation circuit, a negative-phase pulse voltage generation circuit, a first DC power source for supplying a bias for setting a peak value of pulse voltages, a second DC power source to output a variable voltage having a polarity identical to a polarity of toner charge, a first diode having an anode and a cathode connected to a lower potential side of the positive-phase pulse voltage generation circuit and an output terminal thereof, and a second diode having an anode and a cathode connected to the lower potential side of the positive-phase pulse voltage generation circuit and an output terminal thereof. | 07-28-2011 |
| 20120057891 | IMAGE FORMING APPARATUS - An image forming apparatus includes a latent image carrier; a latent image writer to write a latent image on the latent image carrier; a developing unit including a toner carrier having first and second electrodes insulated via an insulator member and a voltage applying unit to apply voltages to the first and second electrodes having a potential difference to generate first electric fields to cause the toner to hop from the toner carrier to the latent image carrier to develop a toner image; and a transfer unit to transfer the developed toner image to a transferring member. When alternating voltages having a same phase and same amplitude are applied to the first and second electrodes to form second electric fields between the latent image carrier and the toner carrier, the toner is discharged from the toner carrier to the latent image carrier in a toner discharge mode. | 03-08-2012 |
| 20120063797 | DEVELOPING DEVICE, IMAGE FORMING APPARATUS, AND IMAGE FORMING METHOD - An image forming apparatus includes a latent image carrier to carry a latent image, a developing device having a toner carrier with first and second electrodes to develop the latent image by transferring the toner to a developing region between the toner carrier and the latent image carrier while causing the toner to hop between the first and second electrodes and attaching the hopping toner to the latent image, a pulsed power supply to output a first periodic pulse voltage having a mean potential the same as a normal toner charge and a second periodic pulse voltage, a smoothing circuit to make the first periodic pulse voltage smooth to generate a direct voltage, and a toner layer thickness regulator member to regulate, on receiving the direct voltage, a thickness of the toner layer in a region between a toner supply position at which toner is supplied and the developing region. | 03-15-2012 |
| 20120063815 | DEVELOPMENT DEVICE, PROCESS CARTRIDGE INCORPORATING SAME, AND IMAGE FORMING APPARATUS INCORPORATING SAME - A development device includes a developer container; a rotary cylindrical developer carrier including an outer electrode including multiple electrode portions arranged in a circumferential direction of the developer carrier, an inner electrode provided on an inner circumferential side of the developer carrier from the outer electrode, an insulation layer disposed between the outer electrode and the inner electrode, and a surface layer; and a bias power source to apply a first bias voltage and a second bias voltage to the inner electrode and the outer electrode, respectively. The first bias power source causes an electrical potential difference that changes with time between the inner electrode and the outer electrode to cause the developer to hop on a circumferential surface of the developer carrier. At least one of the first bias voltage and the second bias voltage has a cyclic waveform in which pulse-on time is reduced. | 03-15-2012 |
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| 20110135587 | Hair Conditioning Composition - The present invention provides an easily-handled hair conditioning composition with a very low water content. The hair conditioning composition of the present invention is a composition comprising: (a) 10 to 90% by mass of one or more components selected from higher alcohols, higher fatty acids, and derivatives thereof, (b) 5 to 35% by mass of a cationic surfactant, and (c) a polyhydric alcohol and/or polyethylene glycol having a melting point of 155° C. or less, characterized in that the endothermic peak of a gel which is formed from (a) and (b) in the composition is 50° C. or more as measured by a differential scanning calorimeter (DSC) and that the water content is 10% by mass or less. | 06-09-2011 |
| 20110165110 | Hair Conditioning Composition And Low Energy Method Of Producing The Same - A hair conditioning composition containing very little water from which a hair conditioner can be easily produced by diluting with water, and a low energy production method thereof. A hair conditioning composition including (a) 10 to 90% by mass of specifically structured higher alcohols and/or derivatives thereof, (b) 5 to 35% by mass of cationic surfactant, and (c) a polyhydric alcohol and/or polyethylene glycol having a melting point of 70° C. or less, wherein the melting point of a gel which is formed from (a) and (b) in the composition is 70° C. or less, the water content is 10% by mass or less, and the molar ratio of (a) to (b) is 2.5 or more to less than 6.0. Also, a low energy method of producing a hair conditioner by melting the hair conditioning composition under heating at the temperature of the melting point of gel or more to 70° C. or less, and diluting it with water in an amount of 3 to 15 times by mass. | 07-07-2011 |
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| 20090311461 | OPTICAL INFORMATION RECORDING MEDIUM - An optical information recording medium is provided and includes a supporting substrate, a light-transmissive protective layer, information recording layers, and at least one interlayer transparent to a laser beam having a wavelength of 400 to 410 nm. Among the information recording layers, one or a plurality of information recording layers other than the information recording layer closest to the supporting substrate each function as a semi-transmissive information recording layer that transmits the laser beam. Some or all of the one or the plurality of semi-transmissive information recording layer include, from the laser beam incident side, a first dielectric portion having a refractive index of 2.4 or more for the wavelength of the laser beam, a recording material portion having a thickness of at least 5.2 nm, a second dielectric portion, a metal portion having a thickness of at least 7 nm, and a third dielectric portion in that order. | 12-17-2009 |
| 20100209653 | OPTICAL INFORMATION RECORDING MEDIUM - An optical information recording medium includes: a supporting substrate; a light-transmitting protective layer which becomes a layer on the incident side of recording and reproducing laser light; and an information recording layer intervening between the supporting substrate and the light-transmitting protective layer, wherein the information recording layer includes a phase-change material layer, a dielectric layer and a metal layer in this order from the incident side of laser light; and the dielectric layer is constituted of, as a main component, (In | 08-19-2010 |
| 20120027979 | OPTICAL RECORDING MEDIUM - An optical recording medium includes a support substrate, and a semi-transmissive recording layer including a first dielectric layer, a semi-transmissive semi-reflective layer, a second dielectric layer, a phase-change recording material layer, and a third dielectric layer which are laminated in that order from the support substrate side. The semi-transmissive semi-reflective layer is composed of silver, and the first dielectric layer includes a composite oxide layer using niobium oxide. | 02-02-2012 |
| 20120027980 | OPTICAL RECORDING MEDIUM - An optical recording medium includes a support substrate and a semi-transmissive recording layer. The semi-transmissive recording layer includes a first dielectric layer, a semi-transmissive semi-reflective layer, a second dielectric layer, a phase change recording material layer, and a third dielectric layer that are sequentially stacked in that order on the support substrate. The semi-transmissive semi-reflective layer contains silver. The second dielectric layer has a stack structure including a lower layer disposed at the interface on the semi-transmissive semi-reflective layer side and an upper layer disposed on the phase change recording material layer side of the lower layer. The lower layer is composed of indium oxide or a composite oxide of indium oxide and tin oxide. The upper layer is composed of tantalum oxide, gallium oxide, zirconium oxide, or niobium oxide. | 02-02-2012 |
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| 20090120900 | MULTI-LAYERED BOTTLE - There is provided a multilayer bottle comprising a barrel portion including an outermost layer, an innermost layer and at least one barrier layer interposed between the outermost layer and the innermost layer, which satisfies the requirements represented by the following formulae (1) to (3) at the same time: | 05-14-2009 |
| 20090237108 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal. | 09-24-2009 |
| 20090277858 | Multilayer Bottle - There is provided a multilayer bottle including an outermost layer and an innermost layer which are each made of a thermoplastic polyester resin, and at least one barrier layer interposed between the outermost layer and the innermost layer. The barrier layer contains at least two components including a polyamide obtained by polycondensing a diamine component containing m-xylylenediamine as a main component with a dicarboxylic acid component containing an α,ω-linear aliphatic dicarboxylic acid as a main component, and a thermoplastic resin having a lower molecular weight than that of the polyamide. The multilayer bottle hardly suffers from delamination upon impact or dropping and, therefore, is not required to have a shape with less irregularities or less bends for preventing the delamination, and further has a large freedom of design choice. | 11-12-2009 |
| 20110248741 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip. | 10-13-2011 |
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| 20090059084 | IMAGE PROCESSING APPARATUS, METHOD THEREOF, AND PROGRAM - An image processing apparatus includes a unit configured to calculate a sum of absolute differences between pixel values of pixels in a block of interest and pixel values of pixels in a reference block, a unit configured to compare sums of absolute differences calculated and to determine a minimum sum of absolute differences thereamong, a unit configured to estimate a motion vector for the pixel of interest using the reference pixel having the minimum sum of absolute differences and the pixel of interest, a unit configured to generate a motion-compensated image by using pixel values of the pixels as pixel values of corresponding pixels in the motion-compensated image, a unit configured to cumulatively add sums of absolute differences, and a unit configured to generate an interpolation image by mixing the pixels and corresponding pixels in the motion-compensated image according to an obtained cumulative-sum result. | 03-05-2009 |
| 20090213273 | APPARATUS AND METHOD FOR MANAGING VIDEO AUDIO SETTING INFORMATION AND PROGRAM - A setting information database associates setting information used to output a video signal or an audio signal with a corresponding viewing condition. A setting information registration unit registers setting information and a corresponding viewing condition which have been received by a setting information reception unit so as to store them in the setting information database. An adequacy determination unit determines the adequacy of recommended setting information to be stored in the setting information database. A condition extraction unit extracts pieces of setting information stored in the setting information database on the basis of a viewing condition supplied from an extraction condition reception unit. A recommendable setting derivation unit derives recommendable setting information from the extracted pieces of setting information. | 08-27-2009 |
| 20090232407 | IMAGE PROCESSING DEVICE, METHOD, AND PROGRAM - An image processing device includes: a step calculator configured to calculate, as a step, a difference in pixel values of pixels in a neighborhood with respect to each pixel in an image; a classifier configured to classify the pixels into classes for areas of the steps; a boundary ratio calculator configured to calculate, as a boundary ratio, a ratio of the number of pixels at a block boundary for each of the classes; and a block noise strength determinator configured to determine, as a block noise strength of the image, the step that is larger than a predetermined threshold and that is at a class having a largest value. | 09-17-2009 |
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| 20090027993 | Semiconductor memory device and data storage method - According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information. | 01-29-2009 |
| 20090167337 | Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof - A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line. | 07-02-2009 |
| 20110241216 | Semiconductor device - A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line. | 10-06-2011 |
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| 20100244904 | Buffer circuit having switch circuit capable of outputing two and more different high voltage potentials - A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages. The buffer includes a logic control circuit, a first MOS transistor provided between a power supply for feeding the first high voltage and an output terminal, the first MOS transistor including a gate receiving a control signal of the first high voltage level outputted from the logic control circuit, and a backgate receiving the first high voltage, a second MOS transistor provided between a power supply for feeding the second high voltage and the output terminal, the second MOS transistor including a gate receiving a control signal of the second high voltage level outputted from the logic control circuit, and a backgate receiving the second high voltage, and a first switch circuit provided between the first MOS transistor and the output terminal and controlled ON/OFF state thereof by the control signal of the second high voltage level. | 09-30-2010 |
| 20110285425 | Buffer circuit having switch circuit capable of outputting two and more different high voltage pontentials - A buffer circuit includes a first power source node receiving a first voltage, a second power source node receiving a second voltage lower than the first voltage, an output node driving the first and second voltage, a first transistor coupled between the first power source node and the output node, the first transistor being controlled by a first voltage swing, a second transistor coupled between the second power source node and the output node, the second transistor being controlled by a second voltage swing smaller than the first voltage swing and a switch circuit coupled between the output node and the second transistor, the switch circuit being controlled by a third voltage swing larger than the second voltage swing. | 11-24-2011 |
