Patent application number | Description | Published |
20090142923 | COPPER GATE ELECTRODE OF LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M | 06-04-2009 |
20100149473 | PIXEL ARRAY AND MANUFACTURING METHOD THEREOF - A pixel array includes a substrate, scan lines, data lines, active devices, first pads, second pads, first wires, second wires, an insulating layer, an organic planarization layer, first pad electrodes, second pad electrodes and pixel electrodes. The substrate has a display area and a non-display area. The scan lines and the data lines are disposed in the display area. The active devices are disposed in the display area and electrically connected to the scan lines and the data lines. The first and second pads are disposed in the non-display area. The first and second wires are disposed in the non-display area and respectively connected to the first and second pads. The organic planarization layer covers the insulating layer. The first and second pad electrodes are disposed on the organic planarization layer in the non-display area. The pixel electrodes are disposed on the organic planarization layer in the display area. | 06-17-2010 |
20110156038 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices. | 06-30-2011 |
20110292331 | PIXEL STRUCTURE AND DISPLAY PANEL HAVING THE SAME - A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line. | 12-01-2011 |
20120092578 | DISPLAY PANEL - A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant. | 04-19-2012 |
20120161136 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) array substrate with few processing steps and simple structure is provided, wherein merely two patterned metal layers are required and a patterned planarization layer is adopted to separate the two patterned metal layers from each other and thereby reduce power loading. In addition, the patterned planarization layer has slots to form height differences so as to separate scan lines from common electrodes to further reduce the power loading. | 06-28-2012 |
20130161604 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain. | 06-27-2013 |
20140042444 | PIXEL STRUCTURE AND FABRICATING METHOD OF PIXEL STRUCTURE - A pixel structure and a fabricating method thereof are provided. An insulating layer and a planar layer are formed on an electrode. The planar layer has a first opening. A conductive layer is formed on the planar layer and filled into the first opening. A patterned photoresist layer having an etching opening is formed. A wet etching process employing the patterned photoresist layer as a mask is performed on the conductive layer to remove the conductive layer disposed above the electrode via the etching opening and etch laterally the conductive layer below the patterned photoresist layer, to form a patterned conductive layer having a second opening. A dry etching process employing the patterned photoresist layer as a mask is performed on the insulating layer to remove the insulating layer disposed above the electrode via the etching opening, to form a patterned insulating layer having a third opening. | 02-13-2014 |