Patent application number | Description | Published |
20090292836 | DATA ACCESS DEVICE AND METHOD FOR COMMUNICATION SYSTEM - A data access device for a communication system includes: a write controller controlled by the host and outputting a write pointer; a read controller controlled by the write pointer and outputting a read pointer; a download timing controller comparing the write and read pointers to determine a timing of downloading data from the host, and including a pointer difference calculator and a comparator, the pointer difference calculator calculating a distance between the write and read pointers to obtain a pointer difference, the comparator outputting a download status indication according to the pointer difference and a first predetermined length to provide a basis for changing the write pointer; and a transmit buffer downloading data from the host according to the write pointer and transmitting data to the network interface according to the read pointer. A data access device for a network interface controller and a data access method are also disclosed. | 11-26-2009 |
20090327693 | NETWORK TASK OFFLOAD APPARATUS AND METHOD THEREOF - A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets. | 12-31-2009 |
20110110383 | NETWORK INTERFACE CONTROLLER CAPABLE OF SHARING BUFFERS AND BUFFER SHARING METHOD - The disclosure is a network interface controller (NIC) capable of sharing buffers, which is coupled to a host and a network to make the network connection. The NIC includes a transmitting buffer, a transmitting controller, a receiving buffer, and a receiving controller. The transmitting controller controls the transmitting buffer to transmit the transmission data provided by the host to the network. The receiving controller controls the receiving buffer to transmit the reception data received from the network to the host, and determines a storage capacity of the receiving buffer. When the storage capacity is smaller than a set value, the receiving controller transmits a request signal to the transmitting controller, the transmitting controller generates a response signal according to the request signal and a status signal corresponding to the transmitting buffer, and the receiving controller controls whether reception data is stored in the transmitting buffer according to the response signal. | 05-12-2011 |
20110283068 | MEMORY ACCESS APPARATUS AND METHOD - A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner. | 11-17-2011 |
20150035551 | CELL CHARACTERIZATION WITH MILLER CAPACITANCE - A method for cell characterization with Miller capacitance includes characterizing input capacitance of an input of a first stage in a cell by considering a first current transition at the input of the first stage up to a first stop time. The first stop time occurs during the first current transition exhibits a substantial tail portion contributed by the later of a first input voltage transition and a first output voltage transition reaching a corresponding steady state voltage. The first input voltage transition is associated with the input of the first stage. The first output voltage transition is associated with an output of the first stage coupled to the input through a capacitor. | 02-05-2015 |
20150067624 | SYSTEM AND METHOD FOR LEAKAGE ESTIMATION FOR STANDARD INTEGRATED CIRCUIT CELLS WITH SHARED POLYCRYSTALLINE SILICON-ON-OXIDE DEFINITION-EDGE (PODE) - A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current. | 03-05-2015 |
20150091543 | POST-SILICON TUNING IN VOLTAGE CONTROL OF SEMICONDUCTOR INTEGRATED CIRCUITS - A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data. | 04-02-2015 |
20150095864 | POWER RAIL FOR PREVENTING DC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met. | 04-02-2015 |
20150095873 | METAL LINES FOR PREVENTING AC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit. | 04-02-2015 |