Patent application number | Description | Published |
20080268557 | METHOD FOR MEASURING A THIN FILM THICKNESS - A method for measuring a thin film thickness is provided. The method includes the following steps: providing a plurality of structures, each including a semiconductor substrate, a thin film, and a metal layer; measuring resistances of the metal layers of the plurality of structures and thicknesses of the thin films of the plurality of structures to obtain a plurality of resistance values and a plurality of corresponding thickness values; establishing a thickness-resistance table based on the plurality of resistance values and thickness values; providing a structure to be tested including a semiconductor substrate, a thin film, and a metal layer; and measuring resistance of the metal layer of the structure to be tested to determine a thickness value of the thin film of the structure to be tested according to the thickness-resistance table. | 10-30-2008 |
20100276764 | SEMICONDUCTOR STRUCTURE WITH SELECTIVELY DEPOSITED TUNGSTEN FILM AND METHOD FOR MAKING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially. | 11-04-2010 |
20100279498 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially. | 11-04-2010 |
20100314765 | INTERCONNECTION STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MAKING THE SAME - An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud. | 12-16-2010 |
20120267760 | CAPACITOR AND MANUFACTURING METHOD THEREOF - A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer. | 10-25-2012 |
20120270408 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate. | 10-25-2012 |
20120270411 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N | 10-25-2012 |
20120273948 | INTEGRATED CIRCUIT STRUCTURE INCLUDING A COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a barrier layer including a titanium nitride layer and a method for fabricating the same are disclosed. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer connected to the copper layer, wherein the barrier layer comprises a first layer including a tantalum layer and a tantalum nitride layer and a second layer including a titanium nitride layer, the first layer contacts the copper layer and is disposed between the copper layer and the second layer, and the barrier layer has a recess correspondingly above the copper layer; and forming an aluminum (Al) layer disposed in the recess. | 11-01-2012 |
20120273950 | INTEGRATED CIRCUIT STRUCTURE INCLUDING COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a CuSiN layer and a method for fabricating the same are provided. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer including a CuSiN layer on the copper layer; forming a wetting layer on the barrier layer; and forming an aluminum (Al) layer on the wetting layer. | 11-01-2012 |
20120276730 | METHODS FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; performing an oxygen treating process to implant oxygen into the nitride layer; and performing a thermal treating process to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure. | 11-01-2012 |
20120276731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure. | 11-01-2012 |
20130052820 | METHOD OF FORMING CONDUCTIVE PATTERN - A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other. | 02-28-2013 |
20130071978 | FABRICATING METHOD OF TRANSISTOR - A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain. | 03-21-2013 |
20130071992 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer. | 03-21-2013 |
20130140682 | BURIED WORD LINE AND METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - A buried word line includes a substrate having thereon a recessed trench, an insulating layer on a bottom surface and a sidewall of the recessed trench, and a lining layer in the recessed trench. The lining layer has a cleaned surface that is cleaned by a cleaning solution comprising HF or H3PO4. A tungsten layer is selectively deposited on the cleaned surface of the lining layer. | 06-06-2013 |
20130241063 | THROUGH-SILICON VIA AND FABRICATION METHOD THEREOF - A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature. | 09-19-2013 |
20130292799 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer. | 11-07-2013 |
20130328202 | THROUGH-SILICON VIA AND FABRICATION METHOD THEREOF - A through silicon via (TSV) structure including a semiconductor substrate; a first inter-metal dielectric (IMD) layer on the semiconductor substrate; a cap layer overlying the IMD layer; a conductive layer extending through the cap layer, the first IMD layer and into the semiconductor substrate; a tungsten film capping a top surface of the conductive layer; a second IMD layer overlying the cap layer and covering the tungsten film; and an interconnect feature in the second IMD layer. | 12-12-2013 |