Kuo, Hsinchu County
Chao-Yang Kuo, Hsinchu County TW
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20150234497 | ELECTRODE OF SELF-CAPACITIVE TOUCH PANEL UTILIZING SERPENTINE TRACE TO INCREASE RESISTANCE - An electrode of a self-capacitive touch panel is provided. The electrode, coupled to a control circuit of the self-capacitive touch panel via a conducting wire, includes: a serpentine portion, having a first side; a main portion, having a second side; and a connecting portion, connected to the first side and the second side to connect the serpentine portion and the main portion. A length of the connecting portion is smaller than a length of the first side and a length of the second side. | 08-20-2015 |
Cheng Cheng Kuo, Hsinchu County TW
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20110241207 | DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION - Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure. | 10-06-2011 |
20120115073 | SUB-RESOLUTION ROD IN THE TRANSITION REGION - The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature. | 05-10-2012 |
Chen-Shen Kuo, Hsinchu County TW
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20150303362 | Ceramic Substrate and Semiconductor Package Having the Same - A ceramic substrate is provided, including: a board having a first surface and a second surface opposing the first surface; first electrical contact pads disposed on the first surface; second electrical contact pads disposed on the second surface; conductive pillars disposed in the board and connecting the first surface and the second surface to electrically connect the electrical contact pad and the second electrical contact pad; a first heat conductive pad disposed on the first surface; a second heat conductive pad disposed on the second surface; and a heat conductive pillar disposed in the board and connecting the first surface and the second surface to contact and be coupled with the first heat conductive pad and the second heat conductive pad, wherein the heat conductive pillar has a width greater than or equal to widths of the conductive pillars and greater than or equal to 300 micrometers. | 10-22-2015 |
20150305201 | Carrier and Package Having the Carrier - A carrier is disclosed, including: a main body having a first surface and a second surface opposing the first surface; a conductive part formed on the first surface of the main body; and a plurality of heat conductors that are not in contact with the conductive part and penetrate the main body to connect the first surface with the second surface. Therefore, heat generated by electronic elements can be effectively dissipated outside to improve the functionality and lifetime of electronic elements. | 10-22-2015 |
20160049372 | Ceramic substrate, package substrate, semiconductor chip package component and manufacturing method thereof - A method for manufacturing a ceramic substrate is characterized in using a preformed trench, a patterned protective layer and a sand blasting process to manufacture a cavity in a ceramic substrate and control the cavity size and shape of the ceramic substrate. The ceramic substrate is collocated with a base substrate to form a package substrate for packaging a semiconductor chip. The manufacturing method set forth above can lower the manufacturing cost and raise the accuracy of the size and shape of the cavity of the ceramic substrate. The abovementioned method can reduce the fabrication cost and increase the precision of the shape and size of a ceramic substrate. | 02-18-2016 |
Chester Kuo, Hsinchu County TW
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20100096746 | PACKAGE MODULE STRUCTURE OF COMPOUND SEMICONDUCTOR DEVICES AND FABRICATING METHOD THEREOF - A compound semiconductor device package module structure includes a heat dissipation film, a dielectric layer, a plurality of compound semiconductor dies, means for mounting the compound semiconductor dies on the heat dissipation film, and a transparent encapsulation material. The dielectric layer includes a plurality of openings formed on the heat dissipation film. The compound semiconductor dies are placed on the heat dissipation film in the openings, and adjacent two compound semiconductor dies are separated by the dielectric layer. The transparent encapsulation material covers the compound semiconductor dies. | 04-22-2010 |
20110068358 | PHOTOELECTRIC DEVICE, METHOD OF FABRICATING THE SAME AND PACKAGING APPARATUS FOR THE SAME - A method for fabricating a photoelectric device initially provides a ceramic substrate comprising a thermal dissipation layer on a bottom layer of the ceramic substrate, an electrode layer on the top surface of the ceramic substrate, and a reflective structure in cavities of the ceramic substrate. Next, a plurality of photoelectric dies is disposed on the top surface of the ceramic substrate. Then, a first packaging layer is formed on the top surfaces of the photoelectric dies. Next, the ceramic substrate is placed between an upper mold and a lower mold. Finally, a plurality of lenses is formed on the top surface of the first packaging layer by using an injection molding technique or a transfer molding technique. | 03-24-2011 |
Chia-Hui Kuo, Hsinchu County TW
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20150036018 | METHOD AND APPARATUS FOR TUNING CAMERA CORRECTION SETTING FOR CAMERA MODULE - A camera tuning circuit has a first storage space, a second storage space and a controller. The first storage space stores a first reference camera correction setting for a reference camera module under a first color temperature. The second storage space stores a second reference camera correction setting for the reference camera module under a second color temperature, wherein the second color temperature is different from the first color temperature. The controller receives a default camera correction setting of a target camera module, the first reference camera correction setting, and the second reference camera correction setting, and generates a tuned camera correction setting for the target camera module according to the default camera correction setting, the first reference camera correction setting, and the second reference camera correction setting. | 02-05-2015 |
Chia-Ming Kuo, Hsinchu County TW
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20130068842 | RFID Tag Structure Having Anti-Reuse Function and Manufacture Method Thereof - The present invention provides a RFID tag structure having anti-reuse function, comprising a substrate; a pattern formed on a surface of the substrate; and an adhesive layer provided on a surface of the pattern which is not in contact with the substrate, wherein the adhesive forces of the adhesive layer are stronger than the binding strengths generated between the pattern and the substrate, and the adhesive layer is capable of being adhered on an article to be adhered and a RFID tag is formed thereby; when the RFID tag is separated from the article to be adhered, the substrate is released from the article to be adhered, the pattern and the adhesive layer are still remained on the article to be adhered, thereby preventing the RFID tag from being reused and fulfilling the objective of anti-reuse and anti-counterfeit. The present invention also provides a manufacture method thereof. | 03-21-2013 |
Chia-Yuan Kuo, Hsinchu County TW
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20150377926 | POSITIONER OF PROBE CARD AND PROBE HEAD OF PROBE CARD - A positioner and a probe head of a probe card are provided. The positioner has a main opening, a first sub-opening, a second sub-opening, a third sub-opening, a fourth sub-opening, a first positioning portion, a second positioning portion, a first elastic portion and a second elastic portion. The first sub-opening, the second sub-opening, the third sub-opening, and the fourth sub-opening are sequentially arranged at the periphery of the main opening and are communicated to the main opening. A stiffness of the first positioning portion and a stiffness of the second positioning portion are higher than a stiffness of the first elastic portion and a stiffness of the second elastic portion. | 12-31-2015 |
Chien-Liang Kuo, Hsinchu County TW
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20150042393 | LEVEL SHIFTER - A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal. The latch circuit is coupled to the input stage circuit through a first output terminal and a second output terminal, and determining steady-state levels of the first and the second output terminals according to the input signal. The transient speed-up circuit is coupled to the first and the second output terminals. When the transient speed-up circuit determines the first and the second output terminals are at the same logic level, the transient speed-up circuit accelerates the positive edge transition of the first or the second terminals. | 02-12-2015 |
Chih-Cheng Kuo, Hsinchu County TW
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20140177758 | TIMING RECOVERY APPARATUS AND METHOD - A timing recovery apparatus for compensating a sampling frequency offset of an input signal is provided. The timing recovery apparatus includes a timing error corrector configured to generate an output signal according to the input signal and a calibration signal, a gain controller configured to adjust at least one of a signal edge low-frequency error component and a signal edge high-frequency error component of the output signal and accordingly generate an adjusted signal, a timing error detector configured to generate an error signal according to the adjusted signal, and a calibration signal generator coupled to the timing error detector and the timing error corrector, for generating the calibration signal according to the error signal and outputting the calibration signal to the timing error corrector to compensate the sampling frequency offset of the input signal. | 06-26-2014 |
20140355659 | RECEIVING APPARATUS AND METHOD FOR ACCELERATING EQUALIZATION CONVERGENCE - A receiving apparatus applied to a receiving end of a communication device having an equalizer is provided. The receiving apparatus includes a filter and a channel estimator. The filter filters a received signal to reduce a multipath effect of the received signal and outputs a filtered signal. The channel estimator performs channel estimation on the received signal to generate an estimation result. The estimation result is for determining which of the received signal and the filtered signal is to be selected and sent to the equalizer. | 12-04-2014 |
20140362963 | CORRECTING APPARATUS FOR TIMING RECOVERY OF RECEIVER AND METHOD THEREOF - A correcting apparatus for timing recovery of a receiver is provided. The receiver includes a timing recovery module that outputs a first symbol and a second symbol. The correcting apparatus includes: a channel impulse response module, configured to generate a first set of peak times and a second set of peak times according to the first symbol and the second symbol, respectively; and a calculation module, configured to calculate a correction signal according to a relationship between the first and second sets of peak times and to send the correction signal to the timing recovery module. | 12-11-2014 |
20150124913 | CIRCUIT AND METHOD FOR CALCULATING ERROR OF SAMPLING CLOCK, AND SIGNAL RECEIVING CIRCUIT AND METHOD - A method for calculating an error of a sampling clock is provided. The sampling clock is used for sampling a signal to generate a first sample data group and a second sample data group. Each of the first and second sample data groups includes a header having a predetermined sequence. The method includes: performing a correlation operation on the first and second sample data groups with data of the predetermined format to obtain first and second correlation results, respectively; comparing the first and second correlation results to generate a sample data group offset; and generating the error of the sampling clock according to the sample data group offset and a time difference between the first and second sample data groups. | 05-07-2015 |
Chih-Chia Kuo, Hsinchu County TW
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20100053190 | Method and Apparatus for Signal Compensation in an Image Display Device - A signal compensation method for an image display device includes deriving an input signal, which is a product of an original signal and a gain value, comparing the input signal with a threshold range for generating a comparison result, generating a difference value according to the comparison result, and generating an output signal according to the original signal, the difference value and a weighting value. | 03-04-2010 |
20100060670 | Method and Apparatus of Color Adjustment for a Display Device - A color adjustment method for a display device includes receiving a composite video signal including a first chrominance signal and a first luminance signal, generating a hue signal and a saturation signal according to at least the first chrominance signal, generating an intensity gain parameter according to the hue signal and the saturation signal, generating a saturation gain parameter according to the hue signal, generating a hue deviation parameter according to the hue signal, adjusting the first luminance signal according to the intensity gain parameter for generating a second luminance signal, and adjusting the first chrominance signal according to the hue deviation parameter and a mixed parameter generated according to the saturation gain parameter, for generating a second chrominance signal. | 03-11-2010 |
20100277642 | Text Protection Device and Related Motion Adaptive De-interlacing Device - A text protection device for de-interlacing operation includes a pixel value difference calculation unit, a text detection unit and a vertical interpolation unit. The pixel value difference calculation unit is utilized for calculating pixel value differences of a plurality of pixels of a field according to a position of a target pixel being inserted into the field. The plurality of pixels forms a detection area corresponding to the target pixel. The text detection unit is utilized for determining whether the detection area includes a text stroke and determining whether the target pixel is located within a range of the text stroke to generate a text detection signal. The vertical interpolation unit performs a vertical interpolation operation to generate a pixel value of the target pixel according to the text detection signal. | 11-04-2010 |
20100289961 | IMAGE PROCESSING CIRCUIT AND IMAGE PROCESSING METHOD THEREOF - An image processing circuit and an image processing method thereof are disclosed. A difference value adaptor of the image processing circuit produces a weighing value and a flag value corresponding to the pixel according to the pixel difference value of each pixel of an input video signal. The image processing circuit judges which area among a first area, a second area and a third area the pixel difference value of each pixel falls in according to the flag value. The image processing circuit performs a low-pass filtering processing on the pixel having the pixel difference value falling in the first area, performs a high-pass filtering processing on the pixel having the pixel difference value falling in the second area and performs a luminance transient improvement processing (LTI processing) on the pixel having the pixel difference value falling in the third area. | 11-18-2010 |
20100303376 | CIRCUIT AND METHOD FOR PROCESSING IMAGE - A circuit and a method for processing an image are provided. The circuit includes a weighting circuit and a sharpening circuit. The weighting circuit includes at least two adapters and a weight decider. The weighting circuit receives an input image. Each of the adapters respectively generates a weight according to an image property of the input image. The weight decider performs a logical calculation according to the weights generated by the adapters to generate a total weight. The sharpening circuit performs an image sharpening process on the input image according to the total weight to generate an output image. | 12-02-2010 |
20110243441 | Image Transient Improvement Apparatus - An image transient improvement apparatus for suppressing aliasing patterns in an image is disclosed. The image transient improvement apparatus includes a limit detector for detecting a maximum gray level and a minimum gray level of a plurality of pixels of a sub-zone of the image, a filter for acquiring a frequency component of the plurality of pixels at a specific frequency, a weighted second-order derivative detector for calculating a plurality of second-order derivatives of the plurality of pixels and accordingly generating a gain, a multiplier for multiplying the frequency component by the gain to generate an amplified frequency component, an adder for adding the amplified frequency component to the plurality of pixels to generate an adding result, and a limiter for converting the adding result to a transient improved sub-zone according to the maximum gray level and the minimum gray level. | 10-06-2011 |
20120082394 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - An image processing apparatus including an image detecting unit, an image interpolating unit and an image blending unit is provided. The image detecting unit detects a pixel difference value of an image frame and a previous image frame or a next image frame thereof and outputs a weight value according to the pixel difference value. The image interpolating unit interpolates a pixel value of the image frame in an intra-field interpolation method and an inter-field interpolation method. The image blending unit blends the pixel value interpolated in the intra-field interpolation method and the pixel value interpolated in the inter-field interpolation method to restore the image frame according to the weight value. An image processing method is also provided. | 04-05-2012 |
20120140116 | IMAGE ADJUSTING CIRCUIT AND IMAGE ADJUSTING METHOD - An image adjusting method is adapted to an image adjusting circuit. The image adjusting method includes following steps. An image signal is received and up-sampled to generate a first up-sampled image signal and a second up-sampled image signal. The first up-sampled image signal includes interpolated pixels and original pixels. Values of the interpolated pixels and the original pixels are detected, and a weight value is outputted according to the detection result. Whether the values of the interpolated pixels are adjusted or not is determined based on the detection result. According to the weight value, the second up-sampled image signal and the adjusted first up-sampled image signal are mixed to output a mixed image signal. An image adjusting circuit is also provided. | 06-07-2012 |
20140161350 | COLOR TRANSLATION METHOD AND COLOR TRANSLATION APPARATUS - A color translation method and a color translation apparatus adapted to map a data point from a first color space to a second color space are provided. At least four color axes coordinating with a plurality of first reference points and a plurality of second reference points corresponding to the first reference points are used to divide the first color space and second color space into a plurality of first sub-spaces and a plurality of second sub-spaces. A target first sub-space where the data point is located is found, and then a corresponding target second sub-space is also found. According to a positional relationship between the data point and the first reference points which define the target first sub-space, an interpolation operation is applied to the second reference points which define the target second sub-space so as to obtain a mapped point in the second color space. | 06-12-2014 |
20150256804 | ARTIFACT REDUCTION METHOD AND APPARATUS AND IMAGE PROCESSING METHOD AND APPARATUS - Artifact reduction method and apparatus, and image processing method and apparatus are provided. The artifact reduction apparatus includes a scaling-down unit, a buffer unit, an artifact detection unit, a scaling-up unit and a filter unit. The scaling-down unit scales down a resolution of a current original image frame to obtain a current low-resolution image frame. The artifact detection unit performs an artifact detection to the current low-resolution image frame to obtain low-resolution weights in accordance with a relation of the current low-resolution image frame and a previous low-resolution image frame provided by the buffer unit. The scaling-up unit scales up a number of the low-resolution weights to obtain a high-resolution weights. By using the high-resolution weights, the filter unit performs an image processing procedure to the current original image frame for reducing artifact of the current original image frame and obtaining an adjusted image frame. | 09-10-2015 |
Chih-Chung Kuo, Hsinchu County TW
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20140114663 | GUIDED SPEAKER ADAPTIVE SPEECH SYNTHESIS SYSTEM AND METHOD AND COMPUTER PROGRAM PRODUCT - According to an exemplary embodiment of a guided speaker adaptive speech synthesis system, a speaker adaptive training module generates adaptation information and a speaker-adapted model based on inputted recording text and recording speech. A text to speech engine receives the recording text and the speaker-adapted model and outputs synthesized speech information. A performance assessment module receives the adaptation information and the synthesized speech information to generate assessment information. An adaptation recommendation module selects at least one subsequent recording text from at least one text source as a recommendation of a next adaption process, according to the adaptation information and the assessment information. | 04-24-2014 |
20140188482 | VOICE CONTROL METHOD, DEVICE, AND RECORDING MEDIUM FOR THE SAME - A voice control method is provided. At least one object name-action prompt correspondence document is received and processed into an object name-action prompt correspondence document set that defines at least one object name and at least one corresponding action prompt. The object name-action prompt correspondence document set is processed to establish an object name-action prompt correspondence list. A voice is recognized as one or multiple voice recognition results to generate one or multiple corresponding candidate object names. At least one corresponding candidate action prompt is outputted according to the candidate object name(s) and the object name-action prompt correspondence list. A selected action prompt is received, and a module providing the selected action prompt is requested to execute an operation. | 07-03-2014 |
20150179171 | DEVICE AND METHOD FOR GENERATING RECOGNITION NETWORK - A recognition network generation device, disposed in an electronic device, comprising: an operation record storage device storing a plurality of operation records of the electronic device, wherein each of the operation records includes operation content executed by the electronic device and device peripheral information detected by the electronic device when the electronic device executes the operation content; an activity model constructor classifying the operation records into a plurality of activity models according to all the device peripheral information of the operation records; an activity predictor selecting at least one selected activity model according to the degree of similarity between each of the activity models and a current device peripheral information detected by the electronic device; and a weight adjustor adjusting the weights of a plurality of recognition vocabularies, wherein the recognition vocabularies correspond to all the operation content of the at least one selected activity model. | 06-25-2015 |
20150269930 | SPOKEN WORD GENERATION METHOD AND SYSTEM FOR SPEECH RECOGNITION AND COMPUTER READABLE MEDIUM THEREOF - In a spoken word generation system for speech recognition, at least one input device receives a plurality of input signals at least including at least one sound signal; a mode detection module detects the plurality of input signals; when a specific sound event is detected in the at least one sound signal or at least one control signal is included in the plurality of input signals, a speech training mode is outputted; when no specific sound event is detected in the at least one sound signal and no control signal is included in the plurality of input signals, a speech recognition mode is outputted; a speech training module receives the speech training mode and performs a training process on the audio segment and outputs a training result; and a speech recognition module receives the speech recognition mode, and performs a speech recognition process and outputs a recognition result. | 09-24-2015 |
Chih-Ming Kuo, Hsinchu County TW
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20130022830 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon. | 01-24-2013 |
20130027172 | METHOD FOR FABRICATING A CARRIER WITH A THREE DIMENSIONAL INDUCTOR AND STRUCTURE THEREOF - A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots. | 01-31-2013 |
20130075860 | METHOD FOR FABRICATING A THREE-DIMENSIONAL INDUCTOR CARRIER WITH METAL CORE AND STRUCTURE THEREOF - A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures. | 03-28-2013 |
20130127578 | METHOD FOR FABRICATING A THREE-DIMENSIONAL INDUCTOR CARRIER WITH METAL CORE AND STRUCTURE THEREOF - A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures. | 05-23-2013 |
20130181346 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130183823 | BUMPING PROCESS - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130193570 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
20130196498 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
20130213702 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon. | 08-22-2013 |
20130249070 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film. | 09-26-2013 |
20130334671 | SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREOF - A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound. | 12-19-2013 |
20130334681 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate. | 12-19-2013 |
20140008111 | CARRIER WITH THREE-DIMENSIONAL CAPACITOR - A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal. | 01-09-2014 |
20140021601 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps. | 01-23-2014 |
20140027905 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate. | 01-30-2014 |
20140035125 | SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers. | 02-06-2014 |
20140035126 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers. | 02-06-2014 |
20140117540 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers. | 05-01-2014 |
20140120715 | SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers. | 05-01-2014 |
20140141606 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps. | 05-22-2014 |
20140217578 | SEMICONDUCTOR PACKAGE PROCESS AND STRUCTURE THEREOF - A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state. | 08-07-2014 |
Chin Piao Kuo, Hsinchu County TW
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20130135896 | PLANAR LIGHT SOURCE DEVICE AND METHOD OF MANUFACTURING SAME - A planar light source device, comprising: a light guide plate, with its upper surface and lower surface as a first surface and a second surface; at least a light strip, on which is provided with a plurality of light-emitting-diodes (LEDs), said light strip is located on a side of said light guide plate, and said LEDs are disposed in said light guide plate to emit light; a reflective plate, disposed outside said second surface to reflect light; and a diffusion plate, disposed outside said first surface to scatter light reflected by said reflective plate. Since in manufacturing said light guide plate, said light-emitting-diodes (LEDs) are placed in a mold in advance, so that LEDs and said light guide plate form integrally, hereby avoiding lose of light, and raising efficiency of said planar light source device. | 05-30-2013 |
Chin-Wei Kuo, Hsinchu County TW
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20140070366 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided. | 03-13-2014 |
Feng-Jung Kuo, Hsinchu County TW
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20110242031 | DISPLAY DEVICE WITH TOUCH FUNCTION AND 2D SENSING METHOD THEREOF - A display device with a touch function is provided. The display device includes a display panel and a touch panel. The display panel has a plurality of image scan lines, and the image scan lines are respectively activated by a plurality of scan signals generated by a gate driver according to a time sequence. The touch panel has a plurality of touch scan lines and a plurality of touch sensing lines, wherein the touch scan lines and the touch sensing lines are disposed crossing each other for sensing a touched position. The gate driver also provides a plurality of touch scan signals to the touch scan lines according to a time sequence. | 10-06-2011 |
20140126566 | Data Transmission System and Method - A data transmission system is utilized in a Mobile Industry Processor Interface (MIPI). A master device includes a control module for generating a control signal according to a feedback signal. A packet encoding module is coupled to the control module for encoding an original packet to be a transmission packet according to the original packet and the control signal to process a transmission operation. A slave device includes a packet decoding module for decoding the transmission packet to be the original packet or a related display device signal corresponding to the original packet to a display device. A feedback module is coupled to the packet decoding module for generating the feedback signal to the control module of the master device according to a decoding condition of the control module, so as to switch a transmission mode of the transmission operation. | 05-08-2014 |
20140211888 | MIPI SIGNAL RECEIVING APPARATUS AND METHOD - A signal receiving apparatus and method adapted for receiving a MIPI signal are disclosed. The signal receiving apparatus includes a signal receiver, a selector, a decoding apparatus and a byte boundary searcher. The signal receiver receives a clock signal, and obtains an input data stream according to the clock signal. The selector outputs the input data stream to a first or second output terminal according to a decoding error signal. The byte boundary searcher operates a boundary searching operation on the input data stream for generating a byte tuning information, wherein, the signal receiver adjusts the clock according to the byte tuning information for adjusting the input data stream. | 07-31-2014 |
20150042671 | Data Compression System for Liquid Crystal Display and Related Power Saving Method - A data compression system for a liquid crystal display (LCD) includes a host and a drive circuit. The host is utilized for outputting image data in a first data format or a second data format according to an operation mode of the LCD. The drive circuit includes a bypass path, for transmitting the image data according to the operation mode; a compression unit, coupled to the host, for receiving the image data and performing a compression procedure on the image data to generate a compression data according to the operation mode; a storage unit, coupled to the compression unit, for storing the compression data and the image data; a de-compression unit, coupled to the storage unit, for receiving the compression data and performing a de-compression procedure on the compression data to recover the image data according to the operation mode; and a display unit, for displaying the image data. | 02-12-2015 |
Feng-Wei Kuo, Hsinchu County TW
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20150116018 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period. | 04-30-2015 |
Hao-Jan Kuo, Hsinchu County TW
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20100046200 | PRISM SHEET AND BACKLIGHT MODULE - A prism sheet including a transparent substrate, a plurality of prism rods and at least one optical grating structure is provided. The transparent substrate has a first surface and a second surface opposite to the first surface. The prism rods are disposed on the first surface, wherein each of the prism rods extends along a first direction, and the prism rods are arranged along a second direction. The optical grating structure is disposed on the first surface and located between two adjacent ones of the prism rods, wherein the optical grating structure extends along the first direction. In addition, a backlight module using the above-mentioned prism sheet is also provided. | 02-25-2010 |
Hsin Chuan Kuo, Hsinchu County TW
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20120218420 | Apparatus and Method for Calibrating Audio-Visual Signal - An apparatus for calibrating an audio-visual (AV) signal includes a controller for generating a control signal, a controllable filter for selectively filtering the AV signal in response to the control signal to output either the AV signal or a filtered AV signal; and a calibrator for generating a group of calibrating coefficients according to the filtered AV signal and calibrating the AV signal according to the group of calibrating coefficients. | 08-30-2012 |
20140254652 | DIGITAL BROADCASTING RECEIVING SYSTEM AND ASSOCIATED SIGNAL PROCESSING METHOD - A digital broadcasting receiving system is provided. A receiving module receives an M number of symbols each carrying an N number of subcarriers of a control signal. A converting module performs FFT on respective k | 09-11-2014 |
Kuan-Liang Kuo, Hsinchu County TW
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20100199078 | METHOD OF SAFE AND RECOVERABLE FIRMWARE UPDATE AND DEVICE USING THE SAME - A safe and recoverable firmware update method which for a remote embedded electronic device and the device thereof. The method includes reading an update status in a flash memory, and determining the update status. If the update status is “DEFAULT”, a default firmware is executed. If the update status is not “DEFAULT”, the update status is further determined if it is “UPDATED”. If the update status is “UPDATED”, a configuration area is set as “BOOTING” and a new firmware is executed. If the update status is not “UPDATED”, the update status is determined if it is “RUNNEW”. If the update status is “RUNNEW”, a new firmware and an update validation method are executed. If the update validation method gets an update completion validation message, the update status is set as “RUNNEW”. If the update status is not “RUNNEW”, a default firmware is executed. | 08-05-2010 |
Kuei-Wei Kuo, Hsinchu County TW
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20120280680 | HALL INTEGRATED CIRCUIT PACKAGE - A Hall integrated circuit package includes a Hall integrated circuit and a field line guiding module. The Hall integrated circuit and the field line guiding module are assembled together with a connecting pin of the Hall integrated circuit exposed to outside. Magnetic field causing by carrying current of a cable passing through the field line guiding portion will be detected by the Hall integrated circuit more accurately so that current measurement based on the detection of magnetic field will be more sensitive and precise. | 11-08-2012 |
20120280822 | POWER RECEPTACLE CURRENT DISPLAYING AND ALERT DEVICE FOR DETECTING CURRENT STATE OF POWER RECEPTACLE AND RECEPTACLE HAVING THE SAEM - A power receptacle current displaying and alert device comprises a panel; a current sensor being a C silicone steel sheet; a coil winding around the C silicone steel sheet for sensing the current of the power receptacle; a current detector being a Hall IC; the Hall IC being installed at a notch of the C silicone steel sheet so as to detect the current flow in the power wire of the power receptacle; the Hall IC detecting the current electromagnetically; the current detector including an integrated circuit; the integrated circuit can transfer the value about the current state of the power receptacle for displaying; and a display for displaying a current state from the integrated circuit; a sound alarm, a light alarm and a transmitter for alerting the statues of the current of the power receptacle to users. A power receptacle using the device is also provided. | 11-08-2012 |
20140254200 | HIGH RESOLUTION RECTIFIER SUITABLE FOR LOW VOLTAGE SIGNALS - A high resolution rectifier suitable for low voltage signals includes a signal input end connected to a signal source for inputting an original AC current; two amplifiers; one receiving the original AC current from a positive end; and the other receiving the AC current from a negative end; amplification factors of the two amplifiers being reversed to each other; two half wave rectifiers each connected to a respective amplifier selected from the two amplifiers; each half wave rectifier receiving an output from the respective amplifier and removing negative half parts of the input current; and an adder connected to the two half wave rectifiers for adding outputs from the two half wave rectifiers so as to full-wave rectifying of the original AC current. | 09-11-2014 |
Liang-Tai Kuo, Hsinchu County TW
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20150132905 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE HAVING A CAPACITOR WELL DOPING DESIGN WITH IMPROVED COUPLING EFFICIENCY - The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode. | 05-14-2015 |
Ming-Jhih Kuo, Hsinchu County TW
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20160118303 | Method of Forming Source/Drain Contact - A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench. | 04-28-2016 |
Ming-Yu Kuo, Hsinchu County TW
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20150128431 | Magnetic-Field Sensing Method - A magnetoresistive sensing device is provided. A first sensed magnetic-field component in parallel with the x-axis and a second sensed magnetic-field component in parallel with the y-axis of an external magnetic field forming a first inclination angle with the x-axis and a second inclination angle with the y-axis are determined. A virtual plane is defined so as to render a magnetic-field component perpendicular to the virtual plane of the external magnetic field is essentially zero. The first inclination angle and the second inclination angle are adjusted with reference to the virtual plane. An x-axis magnetic-field component in parallel with the x-axis, a y-axis magnetic-field component in parallel with the y-axis and a z-axis magnetic-field component in parallel with the z-axis of the external magnetic field are estimated according to the adjusted first inclination angle, the adjusted second inclination angle, the first sensed magnetic-field component and the second sensed magnetic-field component. | 05-14-2015 |
Min-Shan Kuo, Hsinchu County TW
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20150261369 | TOUCH PANEL HAVING UNEVENLY DISTRIBUTED ELECTRIC FIELD LINES AND CONTROLLING METHOD THEREOF - A touch panel includes a screen, a substrate and a transmitting/receiving unit configured between the screen and the substrate, and having a first surface near the screen and a second surface near the substrate, wherein the size of the first surface is larger than the size of the second surface. | 09-17-2015 |
Pai-Chun Kuo, Hsinchu County TW
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20090321825 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, BIPOLAR-CMOS-DMOS AND METHOD FOR FABRICATING THE SAME - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions. | 12-31-2009 |
20120025308 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING BIPOLAR-CMOS-DMOS - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions. | 02-02-2012 |
Ping-Heng Kuo, Hsinchu County TW
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20130235815 | Method and Apparatus of Enhancing Performance of Downlink Multi-User Multiple-Input-Multiple-Output Transmissions in Wireless Communication System - A method of enhancing performance of downlink multi-user multiple-input-multiple-output transmissions in a wireless communication system comprising a communication device and a network is disclosed. The method comprises generating a feedback report comprising a correlation-based validity threshold (CVT); and transmitting the feedback report from the communication device to the network. | 09-12-2013 |
San-Yi Kuo, Hsinchu County TW
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20150047445 | FINE ADJUSTMENT MECHANISM AND ANGLE ADJUSTING DEVICE HAVING THE FINE ADJUSTMENT MECHANISM - A fine adjustment mechanism includes a connecting unit and a fine-tuning bolt having a bolt shaft and a bolt head. The bolt shaft has a threaded section rotatably engaged with the connecting unit, a non-threaded section between the threaded section and the bolt head, and an annular protrusion projecting outwardly and radially from an outer surface of the non-threaded section and spaced apart from the bolt head. A retaining unit is molded over the fine-tuning bolt and covers the annular protrusion and portions of the non-threaded section which are proximate to two opposite annular end surfaces of the annular protrusion. The fine-tuning bolt is rotatable relative to the retaining unit. The connecting unit is movable along the threaded section when the fine-tuning bolt is rotated. | 02-19-2015 |
Sheng Chang Kuo, Hsinchu County TW
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20130328813 | Unlocking Mechanism for a Touch Screen Device - A method for unlocking a touchscreen device comprises no involvement of pressing a physical button of the touchscreen device. Rather, it employs a pre-defined touchscreen area as the unlocking spot. The location and size of this unlocking spot can be redefined by a user. When this spot is touched by a finger, a counter will start to count numbers. When it passes a pre-defined number threshold, the activation signal will be sent to a micro control unit (MCU) to activate the MCU. In this way, the touchscreen device is unlocked. In addition, a power saving circuit is provided to execute such unlocking function and reduce power consumption. | 12-12-2013 |
20140240274 | Single-layer capacitive touch panel for multi-point sensing - The present invention provides a single-layer capacitive touch panel for multi-point sensing. The capacitive touch panel includes a single patterned touch-sensing layer. When a touch occurs at a certain point on the capacitive touch panel, the generated coupling signal passes through the patterned touch-sensing layer along a determined path so that the coupling signal and thus the location of the certain touch point can be precisely detected. At least two touch points on the capacitive touch panel can be simultaneously detected by enforcing asynchronous scanning at four detecting points at four corners of the capacitive touch panel. Additionally, the single-layer capacitive touch panel can be partitioned into N blocks so as to accomplish the simultaneous sensing of 2×N touch points on the touch panel. | 08-28-2014 |
20150077382 | Touch Circuit Architecture - A projected capacitive touch panel comprises a triangle waveform generator, a plurality of analog switches, a plurality of sample and hold circuits. In addition, it also comprises a single conductive layer and flexible printed connectors. The single conductive layer is made of many sensing lines with high resistance. A triangle waveform is generated by the triangle waveform generator. The triangle waveform is transmitted to the sensing lines via the plurality of analog switches. In a rising stage, the plurality of sample and hold circuits are in their hold state. In a declining stage, the sample and hold circuits are in their sample state. The sample and hold circuit collects voltage deviation depending on resistance deviation on a sensing line. And higher resistance deviation can induce higher deviation voltage in the sensing line. | 03-19-2015 |
Shih-Hsuan Kuo, Hsinchu County TW
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20090010560 | METHOD FOR IMAGE CALIBRATION AND APPARATUS FOR IMAGE ACQUIRING - The present invention relates to a method for image calibration and an apparatus for image acquiring. In the method for image calibration, the image formation position for an image acquiring unit of the apparatus is calibrated according to the relative location of the image acquiring unit to a objective lens of the apparatus, wherein the relative location is determined by calculating the focus index of the image acquired by the image acquiring unit so that a clear and sharp interferogram can be obtained for three dimensional surface profile measuring. In addition, it is possible to obtain a clear and sharp image without any interference fringe outside the coherent range by adjusting the image formation position, which is capable of being utilized for two dimensional defect detection and dimension measurement. | 01-08-2009 |
20090079995 | TILTING ADJUSTABLE SURFACE PROFILOMETER - The invention relates to a tilting adjustable surface profilometer, comprising an apparatus capable of adjusting an image acquiring angle. The apparatus includes two types of frameworks. One is a translation-stage-type tilting adjustable surface profilometer, which is enabled by the translations of two translation stage with the rotation of a rotary rack, a surface profile with an omni-directional angle of a sample can be obtained. The other framework is a surface profilometer with an arc-trajectory tilting apparatus, which is enabled by guiding the surface profilometer to slide along the arc rails with the rotations of the rotary rack, a surface profile with an omni-directional angle of a sample can be obtained. | 03-26-2009 |
20090147334 | MULTI-COLOR OFF-AXIS DIGITAL HOLOGRAPHIC SYSTEM AND THE IMAGING METHOD THEREOF - A multi-color off-axis digital holographic system and the imaging method thereof are disclosed. The multi-color off-axis digital holographic system comprises: a plurality of light emitting diodes, for provide a red (R) beam, a green (G) beam and a blue (B) beam; an interference object lens module, for receiving the R, G, and B beams to generate a beam containing an interference signal; a color imaging device, for receiving the beam containing the interference signal and thus forming a hologram on a surface of the color imaging device by holographic interference while registering the hologram; and a processing device, for receiving the registered hologram form the color imaging device; wherein the processing device perform a zero-filling and reconstructing operations upon the received hologram to obtain phase information of the R, G and B beams. With the aforesaid system, a three-dimensional surface profile with respect to a RG synthetic wavelength is obtained according to a calculation using the phase information of the R and G beams as well as the wavelengths thereof, and similarly, a three-dimensional surface profile with respect to a GB synthetic wavelength is obtained according to a calculation using the phase information of the G and B beams as well as the wavelengths thereof. Thereafter, by performing a calculation using the RG synthetic wavelength and its phase as well as the GB synthetic wavelength and its phase, an overall three-dimensional surface profile with respect to a complete synthetic wavelength is obtained. | 06-11-2009 |
20100321773 | METHOD AND SYSTEM FOR THREE-DIMENSIONAL POLARIZATION-BASED CONFOCAL MICROSCOPY - A method and system for three-dimensional polarization-based confocal microscopy are provided in the present disclosure for analyzing the surface profile of an object. In the present disclosure, a linear-polarizing structured light formed by an optical grating is projected on the object underlying profile measurement. By means of a set of polarizers and steps of shifting the structured light, a series of images with respect to the different image-acquired location associated with the object are obtained using confocal principle. Following this, a plurality of focus indexes respectively corresponding to a plurality of inspected pixels of each image are obtained for forming a focus curve with respect to the measuring depth and obtaining a peak value associated with each depth response curve. Finally, a depth location with respect to the peak value for each depth response curve is obtained for reconstructing the surface profile of the object. | 12-23-2010 |
20110157458 | METHOD AND APPARATUS FOR FOCUSING - The present disclosure provides a method and system for focusing, which modulates a broadband light into a dispersive light having a higher dispersion characteristic and a lower dispersion characteristic, and the dispersion light is projected onto an object so as to form an object light. By means of the filtering and dividing procedure, a first optical spectrum of the dispersion light with respect to the higher dispersion characteristic is utilized to detect a height information of the surface profile of the object. Then, according to the height information, a second optical spectrum of the dispersion light with respect to the lower dispersion characteristic is adjusted to focus onto the object so that an imaging sensing device is capable of sensing the object light with respect to the lower dispersion characteristic, and thereby obtaining a clear and focusing image corresponding to the surface of the object. | 06-30-2011 |
20110261362 | METHOD FOR IMAGE CALIBRATION AND APPARATUS FOR IMAGE ACQUIRING - The present invention relates to a method for image calibration and an apparatus for image acquiring. In the method for image calibration, the image formation position for an image acquiring unit of the apparatus is calibrated according to the relative location of the image acquiring unit to a objective lens of the apparatus, wherein the relative location is determined by calculating the focus index of the image acquired by the image acquiring unit so that a clear and sharp interferogram can be obtained for three dimensional surface profile measuring. In addition, it is possible to obtain a clear and sharp image without any interference fringe outside the coherent range by adjusting the image formation position, which is capable of being utilized for two dimensional defect detection and dimension measurement. | 10-27-2011 |
20120170052 | MEASURING METHOD FOR TOPOGRAPHY OF MOVING SPECIMEN AND A MEASURING APPARATUS THEREOF - A measuring method for topography of moving specimen and a measuring apparatus thereof is disclosed, providing a measuring module that moves along with a testing specimen to narrow relative velocity of the testing specimen and the measuring module so that the measuring module is able to have enough luminous intensity signal at the same position in time, to measure the topography or the thickness of the testing specimen. | 07-05-2012 |
20140092295 | AUTOFOCUS SYSTEM AND AUTOFOCUS METHOD - An embodiment of an autofocus system is provided, including a height detection module, an image detection module, a movement unit and a processing unit. The height detection module is arranged to output a plurality of detection lights along a Z axis direction, wherein each of the detection lights has different focal lengths and different wavelengths such that the height detection module generates a dispersion region along the Z axis direction. The image detection module is arranged to capture an image of the focus position. The movement unit is arranged to move an object along the Z axis direction, wherein the object has an internal surface and an external surface. The processing unit determines whether the external surface and the internal surface are within the dispersion region according to the quantity of the energy peaks of a reflectance spectrum received by the height detection module. | 04-03-2014 |
Shuo-Fen Kuo, Hsinchu County TW
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20120304032 | TEST SYSTEM - A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit. | 11-29-2012 |
20140091812 | METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHINE READABLE MEDIA THEREOF - A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file. | 04-03-2014 |
Shu-Wei Kuo, Hsinchu County TW
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20140133009 | ELECTROWETTING DISPLAY UNIT AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an electrowetting display unit includes the following steps. A first substrate and a second substrate are provided. A first conductive layer is disposed on one side of the first substrate. A second conductive layer is disposed on one side of the second substrate. A polymer layer, which includes a siloxane containing a light-induced cross linkable group and a Si—H bond, is disposed on the first conductive layer. The molecular weight of the monomer of the siloxane is equal to or greater than 5000. A part of the polymer layer is exposed to a light so as to form a plurality of hydrophobic sections. A hydrophilic section is developed by treating a developing agent. The hydrophilic section and the plurality of hydrophobic sections form a pattern layer together. Polar liquid and non-polar liquid are disposed between the pattern layer and the second conductive layer. | 05-15-2014 |
Ting-Long Kuo, Hsinchu County TW
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20100321320 | TOUCH PANEL WITH DISCHARGING FUNCTION - The present invention relates to a touch panel with a discharging function, which comprises a scanning bus, a sensing bus, a control unit, and a discharging circuit. The scanning bus is used for scanning a touch frame. The sensing bus interleaves with the scanning bus, and senses at least a touched location on the touch frame. The control unit is coupled to the scanning bus and the sensing bus | 12-23-2010 |
20130234989 | TOUCH PANEL WITH DISCHARGING FUNCTION - The present invention relates to a touch panel with a discharging function, which comprises a scanning bus, a sensing bus, a control unit, and a discharging circuit. The scanning bus is used for scanning a touch frame. The sensing bus interleaves with the scanning bus, and senses at least a touched location on the touch frame. The control unit is coupled to the scanning bus and the sensing bus | 09-12-2013 |
Wei-Hung Kuo, Hsinchu County TW
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20130100047 | TOUCH DISPLAY DEVICE - A touch display device is provided. The touch display device includes a touch panel, a display panel, an anti-splinted film and a transparent conductive layer. The anti-splinted film is disposed between the touch panel and the display panel. The transparent conductive layer is disposed between the display panel and the anti-splinted film. | 04-25-2013 |
20130293508 | TOUCH PANEL, TOUCH DISPLAY PANEL AND TOUCH DISPLAY APPARATUS - A touch panel capable of assembling to a casing assembly having a conductive protrusion is provided. The touch panel includes a substrate, a decoration pattern layer, a touch sensing device, a reflective protecting electrode, an electrostatic discharge protecting device, a plurality of signal connecting lines, an insulating layer and a protection layer. The decoration pattern layer is located in a periphery region of the substrate and overlapped with the reflective protecting electrode. The electrostatic discharge protecting device is connected to the touch sensing device and the reflective protecting electrode to transmit electrostatic charges to the reflective protecting electrode. The signal connecting lines are overlapped with the decoration pattern layer and electrically connected to the touch sensing device. The protection layer has an opening to expose a portion of the reflective protecting electrode such that the reflective protecting electrode is electrically connected to the conductive protrusion through the opening. | 11-07-2013 |
20140340592 | TOUCH PANEL AND METHOD OF FABRICATING THE SAME - A touch panel includes a substrate, a first patterned conductive layer, a patterned passivation layer, and a second patterned conductive layer. The first patterned conductive layer is located on the substrate, and the first patterned conductive layer includes a plurality of first sensing pads and a plurality of second sensing pads, wherein a gap is formed between adjacent first and second sensing pads. The patterned passivation layer is located on the first patterned conductive layer, and the patterned passivation layer covers the gap and exposes at least a portion of each first sensing pad and at least a portion of each second sensing pad. The second patterned conductive layer is located on the patterned passivation layer. | 11-20-2014 |
Wen-Tong Kuo, Hsinchu County TW
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20100260291 | Carrier Recovery Device and Related Method - A carrier recovery device for a communication receiver is disclosed. The carrier recovery device includes an A/D converter for converting an analog signal received by the communication receiver to a digital signal, a frequency compensator coupled to the A/D converter for compensating frequency of the digital signal according to a carrier frequency offset value, a filter coupled to the frequency compensator for filtering the digital signal to generate an output signal, and a frequency offset estimator coupled to the filter and the frequency compensator for estimating the carrier frequency offset value according to the output signal and providing the carrier frequency offset value to the frequency compensator for implementing carrier recovery. | 10-14-2010 |
Yien-Lin Kuo, Hsinchu County TW
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20130002617 | CONTROL SYSTEM WITH SERIAL INTERFACE - A control system with a serial interface is provided. The control system includes a programmable database, a first driver, at least one second driver, and a controller. A data is written into the programmable database through a programming method. The first driver is coupled to the programmable database via the serial interface. The at least one second driver is coupled with the first driver. The controller is coupled with the serial interface and accordingly coupled to the programmable database and the first driver via the serial interface. The controller captures the data from the programmable database through the serial interface and adjusts parameters of the first driver and the at least one second driver according to the data. | 01-03-2013 |
Yung-Hsin Kuo, Hsinchu County TW
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20150309074 | PROBE CARD - In some embodiments, a probe card includes a PCB, a substrate, a pair of probes, a capacitive device and a first part. The PCB includes a pair of conductive paths through a first surface and a second surface of the PCB. The substrate includes a pair of conductive paths through a first surface and a second surface of the substrate. The conductive paths of the substrate and the corresponding conductive paths of the PCB are coupled between the first surface of the substrate and the second surface of the PCB. The probes and the corresponding conductive paths of the substrate are coupled beyond the second surface of the substrate. The capacitive device is coupled between a first conductive path and a second conductive path through the PCB, the substrate and the probes. The first part is configured beyond the second surface of the PCB, and holds the capacitive device. | 10-29-2015 |