Patent application number | Description | Published |
20130060978 | INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY - Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated. | 03-07-2013 |
20130060986 | INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY - Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated. | 03-07-2013 |
20130151829 | Multi-Chip Initialization Using a Parallel Firmware Boot Process - Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip. | 06-13-2013 |
20150106613 | Multi-Chip Initialization Using a Parallel Firmware Boot Process - Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip. | 04-16-2015 |
20150324138 | DATASET REPLICA MIGRATION - A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica. | 11-12-2015 |
20150324388 | DATASET REPLICA MIGRATION - A method of dataset replica migration is described. An application session may start on a first compute node. A first replica of the dataset to be accessed by the application session may be located on a second compute node. A second replica of the dataset is created to be co-located with the first compute node. A first data block of the dataset may be requested by the application session. The first data block of the first replica of the dataset may be read from the second compute node, when the second replica does not have a copy of the first data block stored in the second replica. The retrieved first data block may be copied to the second replica. The first data block may be read from the second replica, when the first data block is requested by the application session and is contained in the second replica. | 11-12-2015 |