Patent application number | Description | Published |
20080208558 | SYSTEM AND METHOD FOR SIMULATING A MULTIPROCESSOR SYSTEM - Disclosed are techniques for simulating a multiprocessor system is disclosed. Aspects of the present invention are based on such an observation that most memory accesses from different simulated processors do not conflict, and therefore the conservative policy for performing synchronization of all the memory accesses can waste a large amount of processing time. By identifying possibly conflicting memory accesses and only performing synchronization of these memory accesses, the synchronization cost can be reduced considerably. Since the function simulator is able to operate faster and to perform the same memory accesses, the possibly conflicting memory accesses can be identified by first executing the function simulator. | 08-28-2008 |
20080222384 | APPARATUS AND METHOD FOR EXECUTING RAPID MEMORY MANAGEMENT UNIT EMULATION AND FULL-SYSTEM SIMULATOR - A method for performing rapid memory management unit emulation of a computer program in a computer system, wherein address injection space of predefined size is allocated in the computer system and a virtual page number and a corresponding physical page number are stored in said address injection space, said method comprising steps of: comparing the virtual page number of the virtual address of a load/store instruction in a code segment in said computer program with the virtual address page number stored in said address injection space; if the two virtual page numbers are the same, then obtaining the corresponding physical address according to the physical page number stored in said address injection space; otherwise, performing address translation lookaside buffer search, that is, TLB search to obtain the corresponding physical address; and reading/writing data from/to said obtained corresponding physical address. The present invention also provides an apparatus and computer program product for implementing the method described above. | 09-11-2008 |
20080270740 | Full-system ISA Emulating System and Process Recognition Method - Disclosed is a method of recognizing a process in a full-system Industry Standard Architecture (ISA) emulator, comprising the steps of: recognizing a process based on a base address of a page table thereof, recognizing the switch between the processes when said base address of the page table has changed, recognizing the termination of a recorded process when the base address of the page table of the process which tries to modify the page table is not equal to the base address of the page table of the recorded process in the page table. With the recognized process, the binary translation results indexed based on content can be saved into a corresponding process repository, thereby achieving the permanent saving of the translation results and the reuse of translation and optimization on the basis of a previously executed program. Consequently, the overall performance of the full-system Industry Standard Architecture emulator is enhanced. | 10-30-2008 |
20090119089 | METHOD, APPARATUS AND FULL-SYSTEM SIMULATOR FOR SPEEDING MMU SIMULATION - A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system. | 05-07-2009 |
20090144524 | Method and System for Handling Transaction Buffer Overflow In A Multiprocessor System - There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and waiting for any processor having a current transaction to complete its current transaction; re-executing the transaction resulting in the transaction buffer overflow without using the transaction buffer; and when the transaction execution is completed, enabling the peer processors for entering transactions. | 06-04-2009 |
20100161875 | SIMULATOR AND SIMULATING METHOD FOR RUNNING GUEST PROGRAM IN HOST - A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space. The simulator further includes an update tracing device configured for, in response to the update to the guest translation look-aside buffer, perform the update to the host translation look-aside buffer. Also disclosed is a method for running a guest program in a host. | 06-24-2010 |
20100241822 | METHOD AND APPARATUS FOR MANAGING TLB - An apparatus and method for managing a translation look-aside buffer (TLB). The TLB is shared by a plurality of jobs. The method including the steps of: obtaining at least one attribute of each job of the plurality of jobs; assigning a priority level to each job according to at least one attribute of each job; and managing the related TLB entries of each job according to the priority level of each job. The present invention also provides an apparatus for managing TLB corresponding to the above method. The method and apparatus according to the present invention provide an efficient use of the shared TLB. | 09-23-2010 |
20110037981 | WAVE-GUIDE COUPLING SPR SENSOR CHIP AND SENSOR CHIP ARRAY THEREOF - A sensor chip based on the WCSPR effect and an array thereof are disclosed. The sensor chip is a multilayer structure comprising a substrate, a dielectric waveguide layer ( | 02-17-2011 |
20110055522 | REQUEST CONTROL DEVICE, REQUEST CONTROL METHOD AND ASSOCIATED PROCESSORS - A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means and an identifier means. The comparing means is configured to determine if an incoming first queue unit corresponds to the same message with a queue unit that has existed in the request storage module. The identifier setting means is configured to set a save identifier of the queue unit that has existed in the request storage module to indicate not to save a state associated with the message if the first queue unit corresponds to the same message with the queue unit that has existed in the request storage module. According to the technical solution of the invention, the access to the memory caused by saving/loading the states is reduced and thereby increases the processing speed of the processor. | 03-03-2011 |
20110200040 | EXTREMUM ROUTE DETERMINING ENGINE AND METHOD - An embodiment of the invention provides an extremum route determining engine and method. The engine includes a memory for storing a path with a weight in a graph and an extremum route determining logic circuit. The logic circuit includes a path reading section for reading the path in the graph, a writing section for updating the weight of the read path according to a predetermined extremum requirement and writing the path whose weight is updated into the memory, and an extremum route determining section for determining an extremum route. The method includes reading a stored path in a graph, the path having a weight, updating the weight of the read path and writing the path whose weight has been updated into a memory, and determining an extremum route. An embodiment of the invention improves the processing speed of extremum route determination. | 08-18-2011 |
20110246667 | PROCESSING UNIT, CHIP, COMPUTING DEVICE AND METHOD FOR ACCELERATING DATA TRANSMISSION - A processing unit coupled to a bus for accelerating data transmission and a method for accelerating data transmission. The present invention provides a streaming data transmission mode in which a plurality of data blocks are transmitted via one handshake. The present invention employs handshake save policy, when a processing unit sends a request comprising a plurality of data blocks on a bus, a cache or memory will perform address matching to judge whether there is any hit data block. If there is any hit data block, the cache or memory only needs to reply once and then start to continuously transmit the hit data blocks it possesses. Thus, a separate handshake for each data block is no longer needed. | 10-06-2011 |
20110285986 | DETECTION SYSTEM AND METHOD FOR ACQUIRING RESONANCE ANGLE OF SURFACE PLASMON - The present disclosure provides a detection system for acquiring the SPR angle, including a modulatable SPR sensor to be detected; an incident light source apparatus; a photoelectric detector; a narrowband filter system; a modulated signal source for generating an alternating current signal that is used to modulate said modulatable SPR sensor; and a data processing system for recording the corresponding relationship between the incident angle and the intensity of the filtered reflected light and further obtaining the resonance angle of said modulatable SPR sensor. The present disclosure also provides a corresponding detection method for acquiring the SPR angle. | 11-24-2011 |
20120288088 | METHOD AND SYSTEM FOR COMPRESSING AND ENCRYPTING DATA - A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of the original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Various embodiments improve the efficiency of the process of compression and encryption to a great extent by encrypting only the literal portion of the compression result. | 11-15-2012 |
20130007536 | METHOD AND SYSTEM FOR ANALYZING PARALLELISM OF PROGRAM CODE - Methods and systems are provided for analyzing parallelism of program code. According to a method, the sequential execution of the program code is simulated so as to trace the execution procedure of the program code, and parallelism of the program code is analyzed based on the result of the trace to the execution procedure of the program code. Execution information of the program code is collected by simulating the sequential execution of the program code, and parallelism of the program code is analyzed based on the collected execution information, so as to allow programmers to perform parallel task partitioning of the program code with respect to a multi-core architecture more effectively, thus increasing the efficiency of parallel software development. | 01-03-2013 |
20130010949 | METHOD AND SYSTEM FOR COMPRESSING AND ENCRYPTING DATA - A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of said original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Embodiments of the present invention improve the efficiency of the process of compression +encryption to a great extent by means of encrypting only the literal portion of the compression result. | 01-10-2013 |
20130013534 | HARDWARE-ASSISTED APPROACH FOR LOCAL TRIANGLE COUNTING IN GRAPHS - A method and apparatus are provided for hardware-assisted local triangle counting in a graph. The method includes converting vertex relationships of the graph into rule patterns. The method also includes compiling the rule patterns into a binary file, wherein the rule patterns are organized into a finite state machine. The method further includes loading at least a part of the binary file and a search string to be compared there against into a hardware pattern matching accelerator. The method additionally includes receiving a number of matching outputs from the pattern matching accelerator. | 01-10-2013 |
20130013549 | HARDWARE-ASSISTED APPROACH FOR LOCAL TRIANGLE COUNTING IN GRAPHS - A method and apparatus are provided for hardware-assisted local triangle counting in a graph. The method includes converting vertex relationships of the graph into rule patterns. The method also includes compiling the rule patterns into a binary file, wherein the rule patterns are organized into a finite state machine. The method further includes loading at least a part of the binary file and a search string to be compared there against into a hardware pattern matching accelerator. The method additionally includes receiving a number of matching outputs from the pattern matching accelerator. | 01-10-2013 |
20130031553 | HARDWARE ACCELERATION - Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly. | 01-31-2013 |
20130031554 | HARDWARE ACCELERATION - Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread. | 01-31-2013 |
20130326165 | IMPLEMENTATION OF INSTRUCTION FOR DIRECT MEMORY COPY - Embodiments of the present invention relate to a method and system for performing a memory copy. In one embodiment of the present invention, there is provided a method for performing memory copy, including: decoding a memory copy instruction into at least one microcode in response to receipt of the memory copy instruction, transforming the at least one microcode into a ReadWrite Command for each of the at least one microcode, and notifying a memory controller to execute the ReadWrite Command, wherein the ReadWrite Command is executed by the memory controller and comprises at least a physical source address, a physical destination address and a ReadWrite length that are associated with the ReadWrite Command. In another embodiment of the present invention, there is provided a system for performing a memory copy. | 12-05-2013 |
20140012810 | METHOD AND APPARATUS FOR PROCESSING DATABASE DATA IN DISTRIBUTED DATABASE SYSTEM - A method and apparatus for processing database data in a distributed database system, wherein the distributed database system comprises a plurality of computing nodes communicatively coupled via computer networks, the method comprising: creating a plurality of different data replicas wherein each of the data replicas is created in the following way: sorting the database data according to at least one data attribute; generating a row key based on the at least one data attribute; and using the sorted database data with the row key as the data replica, storing different data replicas in different computing nodes; and creating an index for each of the data replicas according to its row key. | 01-09-2014 |
20140012858 | DATA PROCESSING METHOD, DATA QUERY METHOD IN A DATABASE, AND CORRESPONDING DEVICE - A data processing method, data query method in a database, and corresponding device. A data processing, wherein a query request for data records includes information indicating a source and destination IP address, the source IP address including N sections, the destination IP address including M sections, both M and N being positive integers, the method including: determining an index encoding manner for the database, wherein the index is an one-dimensional index including N+M sections, the encoding manner specifying a variation sequence of various sections for the index, at least one of the source IP address and the destination address indicated by the information contained in the possible query request including at least one section having a wildcard character, wherein according to the index, for any possible query requests, successive data records can be obtained as a query result; according to the encoding manner, establishing the index for the data records. | 01-09-2014 |
20140040555 | DATA PROCESSING, METHOD, DEVICE, AND SYSTEM FOR PROCESSING REQUESTS IN A MULTI-CORE SYSTEM - The present disclosure provides a method, device, and system for processing a request in a multi-core system. The method comprises steps of: receiving a request for data by a filter from a requesting unit; comparing an indicator indicative of a logical partition in the request with an indicator indicative of the logical partition in a record of the filter; searching in a unit where the filter is located based on the request and returning a search result to the requesting unit if a comparison result matches; and returning a NONE response to the requesting unit from the filter if the comparison result does not match. | 02-06-2014 |
20140215477 | REALIZING GRAPH PROCESSING BASED ON THE MAPREDUCE ARCHITECTURE - A method and device for realizing graph processing based on the MapReduce architecture is disclosed in the invention. The method includes the steps of: receiving an input file of a graph processing job; predicating a MapReduce task execution time distribution of the graph processing job using an obtained MapReduce task degree-execution time relationship distribution and a degree distribution of the graph processing job; and dividing the input file of the graph processing job into input data splits of MapReduce tasks according to the predicted MapReduce task execution time distribution of the graph processing job. | 07-31-2014 |
20140379956 | MANAGING A TRANSLATION LOOKASIDE BUFFER - Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present invention, a series of operations caused by TLB miss would not need intervening from the hypervisor. On the contrary, when a TLB miss occurs, the hardware directly issues an interrupt to a virtual machine. In this way, the TLB can be efficiently managed by means of a hardware-level auxiliary translation table. Therefore, system overheads can be greatly reduced and system performance can be improved. Methods and apparatuses associated with hardware, hypervisor, and virtual machine in a virtualization enabled system are disclosed, respectively. | 12-25-2014 |