Patent application number | Description | Published |
20150054529 | ELECTRODE STRUCTURE AND CAPACITANCE SENSOR HAVING THE SAME - Provided is an electrode structure for use with a capacitive touch panel to enhance capacitance sensing capability thereof The electrode structure includes electrically conductive fine lines each forming fine line portions, sensing portions, and cross portions. The fine line portions, the sensing portions, and the cross portions together form a latticed pattern. The sensing portions are each disposed between two adjacent ones of the cross portions. Two ends of each said sensing portion are connected to two said cross portions through two fine line portions, respectively. The sensing portions each have a geometric configuration with a short axis and a long axis. The long axis extends in the direction of a corresponding one of the fine line portions. The short axis is of a width larger than a corresponding one of the fine line portions. | 02-26-2015 |
20150054771 | TOUCH PANEL CAPACITIVE SENSOR AND ELECTRODE THEREOF - An electrode of capacitive touch panel sensor includes a plurality of conductive portions, the conductive portions forming a mesh structure. Each of the conductive portions has four curved wires defining a closed region, and each opposite pair of the curved wires has the same opening orientation. | 02-26-2015 |
20150061700 | CAPACITIVE SENSOR - A capacitive sensor applies to a capacitive touch panel and includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of virtual electrodes. The first electrodes each have a first wire portion. The second electrodes are disposed beneath and insulated from the first electrodes, and cross the first electrodes. The second electrodes each have a second wire portion. The virtual electrodes are each disposed between and spaced from two corresponding ones of the first electrodes. The virtual electrodes each include a plurality of continuous portions and a plurality of interrupted portions. The interrupted portions each overlap a corresponding one of the second wire portions of the second electrodes. The width of each of the interrupted portions is less than or equal to the width of the corresponding second wire portion. | 03-05-2015 |
Patent application number | Description | Published |
20130228873 | Apparatus and Method for High Voltage MOS Transistor - A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor. | 09-05-2013 |
20140001607 | PASSIVATION SCHEME | 01-02-2014 |
20140008723 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE WITH LOW PARASITIC BJT GAIN AND STABLE THRESHOLD VOLTAGE - A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure. | 01-09-2014 |
20140159103 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed. | 06-12-2014 |
20140231964 | Multiple Layer Substrate - A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. | 08-21-2014 |
20140264559 | SUPER JUNCTION TRENCH METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type. | 09-18-2014 |
20140322871 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device. | 10-30-2014 |
20150054143 | PASSIVATION STRUCTURE AND METHOD OF MAKING THE SAME - A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer. | 02-26-2015 |
20150061007 | HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING - A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate. | 03-05-2015 |
20150076660 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10. | 03-19-2015 |
20150108542 | BIPOLAR TRANSISTOR STRUCTURE HAVING SPLIT COLLECTOR REGION AND METHOD OF MAKING THE SAME - A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region. | 04-23-2015 |
20150236107 | ULTRA HIGH VOLTAGE SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE CAPABILITIES - A semiconductor device comprises a semiconductor substrate, a first layer over the semiconductor substrate, and a drain region in the first layer. The drain region comprises a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion have a same doping type and a different doping concentration than the drain rectangular portion. | 08-20-2015 |
20150303276 | METHOD OF FABRICATING A LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well. | 10-22-2015 |
20150311070 | Multiple Layer Substrate - A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. | 10-29-2015 |
20150325642 | HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING - A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate. | 11-12-2015 |