Patent application number | Description | Published |
20110062557 | 3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME - A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array. | 03-17-2011 |
20110169126 | In-situ passivation methods to improve performance of polysilicon diode - A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated. | 07-14-2011 |
20110175038 | COATED CARBON NANOFLAKES - Compositions of carbon nanoflakes are coated with a low Z compound, where an effective electron emission of the carbon nanoflakes coated with the low Z compound is improved compared to an effective electron emission of the same carbon nanoflakes that are not coated with the low Z compound or of the low Z compound that is not coated onto the carbon nanoflakes. Compositions of chromium oxide and molybdenum carbide-coated carbon nanoflakes are also described, as well as applications of these compositions. Carbon nanoflakes are formed and a low Z compound coating, such as a chromium oxide or molybdenum carbide coating, is formed on the surfaces of carbon nanoflakes. The coated carbon nanoflakes have excellent field emission properties. | 07-21-2011 |
20120001150 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided. | 01-05-2012 |
20120074367 | COUNTER DOPING COMPENSATION METHODS TO IMPROVE DIODE PERFORMANCE - A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided. | 03-29-2012 |
20120091418 | BIPOLAR STORAGE ELEMENTS FOR USE IN MEMORY CELLS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes (1) a bipolar storage element formed from a metal-insulator-metal (MIM) stack including (a) a first conductive layer; (b) a reversible resistivity switching (RRS) layer formed above the first conductive layer; (c) a metal/metal oxide layer stack formed above the first conductive layer; and (d) a second conductive layer formed above the RRS layer and the metal/metal oxide layer stack; and (2) a steering element coupled to the storage element. Numerous other aspects are provided. | 04-19-2012 |
20120091419 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided. | 04-19-2012 |
20120193756 | DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME - In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided. | 08-02-2012 |
20120228579 | 3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME - A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array. | 09-13-2012 |
20130094278 | Non-Volatile Memory Cell Containing an In-Cell Resistor - A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode. | 04-18-2013 |
20130170283 | LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE - A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode. | 07-04-2013 |
20130175492 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided. | 07-11-2013 |
20130292634 | RESISTANCE-SWITCHING MEMORY CELLS HAVING REDUCED METAL MIGRATION AND LOW CURRENT OPERATION AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer between the MIM stack and the conductor. Numerous other aspects are provided. | 11-07-2013 |
20140284538 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided. | 09-25-2014 |