Kuenzer
Hermann Kuenzer, Freising DE
Patent application number | Description | Published |
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20100207748 | Method for Displaying Information - In a method for displaying information relating to the assignments of functions to a group of freely assignable operating keys in a motor vehicle, a first display step outputs for each operating key of the group a brief description of the respective function assignment, and a second display step outputs for a single selected operating key of the group a more detailed description. In the first display step, the brief descriptions of all operating keys of the group are output side-by-side into screen areas, which essentially are adjacent to each other, in an edge region of a display unit of the motor vehicle. In the second display step, the more detailed description is output into the same edge region of the same display unit such that the more detailed description covers the entire screen area of the brief description of the selected operating key, and the more detailed description at least partially covers the screen area of the brief description of at least one additional operating key. | 08-19-2010 |
Hermann Kuenzer, Berlin DE
Patent application number | Description | Published |
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20090029953 | 18-METHYL-19-NOR-17-PREGN-4-ENE-21,17-CARBOLACTONES, AS WELL AS PHARMACEUTICAL PREPARATIONS THAT CONTAIN THE LATTER - The invention relates to novel 18-methyl-19-nor-17-pregn-4-en-21,17-carbolactones of general formula (I), where Z=O, H | 01-29-2009 |
20090030010 | 3-Amino-pyrazolo[3,4b]pyridines as inhibitors of protein tyrosine kinases, their production and use as pharmaceutical agents - This invention relates to compounds of general formula I | 01-29-2009 |
Jens Kuenzer, Boeblingen DE
Patent application number | Description | Published |
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20080276140 | SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP - A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains. | 11-06-2008 |
20100309734 | METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVICE FOR MONITORING MEMORY CIRCUITS AND CORRESPONDING INTEGRATED CIRCUIT - An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected. | 12-09-2010 |
Jens Kuenzer, Leinfelden-Echterdingen DE
Patent application number | Description | Published |
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20080226008 | Providing Accurate Time-Based Counters for Scaling Operating Frequencies of Microprocessors - The illustrative embodiments provide accurate time-based counters for scaling operating frequencies of microprocessors. A time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment. | 09-18-2008 |
Jens Kuenzer, Boblingen DE
Patent application number | Description | Published |
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20150113346 | ELECTRONIC CIRCUIT HAVING SERIAL LATCH SCAN CHAINS - The invention relates to an electronic circuit ( | 04-23-2015 |