| Patent application number | Description | Published |
|---|
| 20080304337 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 12-11-2008 |
| 20080307163 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 12-11-2008 |
| 20090003054 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 01-01-2009 |
| 20090059668 | Virtual ground array memory and programming method thereof - A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails. | 03-05-2009 |
| 20090059698 | METHOD FOR TESTING MEMORY - A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window. | 03-05-2009 |
| 20090089526 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device. | 04-02-2009 |
| 20090116293 | Memory and method for charging a word line thereof - A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage. | 05-07-2009 |
| 20090154233 | NAND TYPE MEMORY AND PROGRAMMING METHOD THEREOF - A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring. | 06-18-2009 |
| 20090177817 | METHOD AND SYSTEM FOR ENHANCED READ PERFORMANCE IN SERIAL PERIPHERAL INTERFACE - A method for reading data in an integrated circuit includes receiving a read command, which is associated with an enhanced data read, and receiving a first address from a plurality of input/output pins. The method includes receiving a first performance enhancement indicator and determining whether an enhanced read operation is to be performed based on at least information associated with the first performance enhancement indicator. The method includes waiting n clock cycles, where n is an integer, then outputting data from a memory array in the integrated circuit using the plurality of input/output pins concurrently. The method also includes performing an enhanced read operation, if it is determined that the enhanced read operation is to be performed. In an embodiment of the method, performing an enhanced read operation includes receiving a second address and a second performance enhance indicator without receiving a read command. | 07-09-2009 |
| 20090201060 | CLOCK SYNCHRONIZING CIRCUIT - A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit. | 08-13-2009 |
| 20090201725 | MULTI-LEVEL MEMORY CELL PROGRAMMING METHODS - A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage. | 08-13-2009 |
| 20090219759 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 09-03-2009 |
| 20090296496 | METHOD AND CIRCUIT FOR TESTING A MULTI-CHIP PACKAGE - A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells. | 12-03-2009 |
| 20100027339 | PAGE BUFFER AND METHOD OF PROGRAMMING AND READING A MEMORY - A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell. | 02-04-2010 |
| 20100223439 | DATA PROTECTING METHOD AND MEMORY USING THEREOF - A data protecting method for a memory, which comprising a volatile memory and a non-volatile memory for storing data and data protection information, comprises the following steps. Firstly, load the data protection information to the volatile memory from the non-volatile memory. Next, protect the data stored in the memory according to the data protection information stored in the volatile memory. | 09-02-2010 |
| 20110016288 | Serial Flash Memory and Address Transmission Method Thereof - A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock. | 01-20-2011 |
| 20110016291 | Serial Memory Interface for Extended Address Space - An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address. | 01-20-2011 |
| 20110068837 | APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch. | 03-24-2011 |
| 20110069571 | Word Line Decoder Circuit Apparatus and Method - One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. | 03-24-2011 |
| 20110085380 | Method of Programming a Memory - A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an n | 04-14-2011 |
| 20110128791 | Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 06-02-2011 |
| 20110128809 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 06-02-2011 |
