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Kuen-Long
Kuen-Long Chang, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090295419 | MEMORY CHIP AND METHOD FOR OPERATING THE SAME - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 12-03-2009 |
| 20100054045 | Memory and Reading Method Thereof - A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line. | 03-04-2010 |
| 20100149893 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 06-17-2010 |
| 20110038218 | Memory Chip and Method for Operating the Same - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 02-17-2011 |
| 20110216607 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 09-08-2011 |
Kuen-Long Chang, Mucha TW
| Patent application number | Description | Published |
|---|---|---|
| 20100182834 | TWISTED DATA LINES TO AVOID OVER-ERASE CELL RESULT COUPLING TO NORMAL CELL RESULT - Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers. | 07-22-2010 |
Kuen-Long Chang, Mucha-Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100007377 | METHOD AND SYSTEM FOR A SERIAL PERIPHERAL INTERFACE - An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described. | 01-14-2010 |
Kuen-Long Chang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110238939 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit. | 09-29-2011 |
Kuen-Long Tsai, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100284585 | Method for Searching and Constructing 3D Image Database - The present invention relates to methods for searching and constructing a 3D motif image database, wherein said 3D motif image database can be used to understand the connection relationship of a 3D network, e.g. a neural network comprising biological neural networks or artificial neural networks. The searching and constructing methods are applied on the 3D motif image database, a proper computer-aided graphic platform. The database not only facilitates the management of the huge amount of categorized data but also rationally excavates the hidden information cloaked within. | 11-11-2010 |