Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Kudva, NY
Gautam N. Kudva, Horseheads, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110021116 | METHOD FOR PROCESSING AN EDGE OF A GLASS PLATE - A method for beveling a thin glass plate by simultaneously grinding an edge of the glass using multiple abrasive cup wheels, wherein the edge of the glass plate is extended from the fixturing device. The extension of the glass plate allows the glass plate to bend in response to forces applied by the abrasive cup wheels, thereby reducing the sensitivity of the grinding process to variations in position of the abrasive wheels. The axes of rotation of the abrasive wheels are separated by a distance selected to prevent deflection in the glass plate caused by a first abrasive wheel to influence the deflection in the glass plate caused by a second (adjacent) abrasive wheel. | 01-27-2011 |
Gautam Narendra Kudva, Horseheads, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080202167 | Thermal edge finishing - A thermal edge finishing process includes preheating at least one cut edge of a glass sheet, laser finishing the edge to a single full continuous radius from a position orthogonal to the edge and in-plane with the glass sheet while continuing to heat the glass, and localized annealing of the edge to reduce residual stress from the laser/thermal treatment of the edge. By the present process, edge stress is reduced considerably, such as to less than 3000 psi, and more preferably to less than 2500 psi, and to as low as 1000 psi in the first 1 mm along the treated edge. | 08-28-2008 |
| 20100126830 | Gas-Ejecting Bearings for Transport of Glass Sheets - Non-contact, gas-ejecting bearings ( | 05-27-2010 |
| 20110126593 | APPARATUS AND METHOD FOR SEPARATING A GLASS SHEET - A method of separating a moving glass ribbon to form an individual sheet of glass is disclosed comprising a plurality of nosing members that move in a direction and at a speed that the moving glass ribbon is moving. The nosing members can be positioned independently of each other, and can be positioned adjacent to but not in contact with the ribbon during the scoring operation to restrict out-of-plane movement of the glass ribbon (movement substantially transverse to the draw direction of the ribbon) during the separation phase of the process. | 06-02-2011 |
| 20110236630 | Non-Contact Etching of Moving Glass Sheets - Methods and apparatus are disclosed for etching flexible glass sheets ( | 09-29-2011 |
Gautam Narendra Kudva, Horeseheads, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100078295 | Liquid-Ejecting Bearings for Transport of Glass Sheets - Non-contact, liquid-ejecting bearings ( | 04-01-2010 |
Gautam Narendra Kudva, Hoseheads, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20120000749 | Liquid-Ejecting Bearings for Transport of Glass Sheets - Non-contact, liquid-ejecting bearings ( | 01-05-2012 |
Prabhakar Kudva, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080263325 | SYSTEM AND STRUCTURE FOR SYNCHRONIZED THREAD PRIORITY SELECTION IN A DEEPLY PIPELINED MULTITHREADED MICROPROCESSOR - A microprocessor and system with improved performance and power in simultaneous multithreading (SMT) microprocessor architecture. The microprocessor and system includes a process wherein the processor has the ability to select instructions from one thread or another in any given processor clock cycle. Instructions from each, thread may be assigned selection priorities at multiple decision points in a processor in a given cycle dynamically. The thread priority is based on monitoring performance behavior and activities in the processor. In the exemplary embodiment, the present invention discloses a microprocessor and system for synchronizing thread priorities among multiple decision points throughout the micro-architecture of the microprocessor. This system and method for synchronizing thread priorities allows each thread priority to he in sync and aware of the status of other thread priorities at various decision points within the microprocessor. | 10-23-2008 |
| 20090189731 | CROSS POINT SWITCH USING PHASE CHANGE MATERIAL - A cross-point switch and cross-point switch fabric utilizing phase change material, and method of operating the same. The cross-point switch includes a phase change cross-point circuit containing a plurality of terminal nodes connected to a central node. The connections between the terminal nodes and the central nodes are regulated by phase change switches comprised of a phase change material. The phase change switches being controlled by heating elements capable of melting or crystallizing the phase change material in the phase change switch. The heating elements are operated by a separate heating circuit. Each individual heating element is regulated by an individual transistor. | 07-30-2009 |
Prabhakar N. Kudva, Warwick, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100083203 | Modeling System-Level Effects of Soft Errors - Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile. | 04-01-2010 |
Prabhakar N. Kudva, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090049318 | METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT - A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally. | 02-19-2009 |
| 20090070719 | Logic Block Timing Estimation Using Conesize - A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time. | 03-12-2009 |
| 20090070720 | System to Identify Timing Differences from Logic Block Changes and Associated Methods - A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison. | 03-12-2009 |
| 20090089602 | METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT - A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system. | 04-02-2009 |
| 20110154351 | Tunable Error Resilience Computing - An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality of resources for completion of the task in accordance with a level of quality of service in a service level agreement. | 06-23-2011 |
Prabhakar Nandavar Kudva, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110055777 | Verification of Soft Error Resilience - An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance. | 03-03-2011 |
Prabhakar Nandavar Kudva, Warwick, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090193296 | Method and Apparatus for Testing a Full System Integrated Circuit Design by Statistical Fault Injection Using Hardware-Based Simulation - A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC. | 07-30-2009 |