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| 20090252931 | REINFORCED ASSEMBLY CARRIER AND METHOD FOR MANUFACTURING THE SAME AS WELL AS METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGES - A reinforced assembly carrier is provided. A supporting frame made of molding compound is formed on the edge area of the upper surface and/or on the edge area of the lower surface of the assembly carrier thereby enhancing the mechanical strength of the assembly carrier. | 10-08-2009 |
| 20100314744 | SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER EXPOSING PATTERNED DIELECTRIC LAYER, CHIP PACKAGE STRUCTURE INCLUDING THE SUBSTRATE, AND MANUFACTURING METHODS THEREOF - A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die. | 12-16-2010 |
| 20100320610 | SEMICONDUCTOR PACKAGE WITH SUBSTRATE HAVING SINGLE METAL LAYER AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die. | 12-23-2010 |
| 20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 04-14-2011 |
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| 20100171205 | Stackable Semiconductor Device Packages - In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width W | 07-08-2010 |
| 20110057301 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires. | 03-10-2011 |
| 20110062567 | LEADFRAME AND CHIP PACKAGE - A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation. | 03-17-2011 |
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| 20080230882 | CHIP PACKAGE STRUCTURE - A chip package structure includes a die pad of which at least a notch is formed on at least one side and opposite to a mold gate. The die pad contributes to accelerating the injection of an encapsulating material, so as to exhaust the air in the mold in time, before the encapsulating material solidifies during the molding step, thereby overcoming or at least improving the problem of defects such as air bubbles in the encapsulation. | 09-25-2008 |
| 20080230887 | SEMICONDUCTOR PACKAGE AND THE METHOD OF MAKING THE SAME - The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased. | 09-25-2008 |
| 20090278253 | Semi-finished package and method for making a package - The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased. | 11-12-2009 |
