Patent application number | Description | Published |
20100134234 | SHIFT REGISTER APPARATUS - A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof. | 06-03-2010 |
20110024801 | TRANSISTORS HAVING A COMPOSITE STRAIN STRUCTURE, INTEGRATED CIRCUITS, AND FABRICATION METHODS THEREOF - A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate. | 02-03-2011 |
20110042729 | METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 02-24-2011 |
20110108894 | METHOD OF FORMING STRAINED STRUCTURES IN SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material. | 05-12-2011 |
20110147846 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 06-23-2011 |
20120015459 | Thermal Leveling for Semiconductor Devices - A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution. | 01-19-2012 |
20120181625 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions. | 07-19-2012 |
20120205715 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth. | 08-16-2012 |
20120268924 | LIGHT GUIDE UNIT AND OPTICAL DEVICES USING THE SAME - A light guide unit provided in this disclosure is used for performing a reversible optical conversion process on a light source. In an embodiment, the light guide unit is used for converting a planar light source into at least a linear light source, and then further to be converted into one point light source, while allowing beams emitted from the point light source to be guided and shot to a specific position by the use of a light-guiding element. Moreover, in another embodiment, the light guide unit is used for converting at least one point light source into at least a linear light source, and then further to be converted into a planar light source for emitting light. The light guide unit can be adapted for various applications, such as optical devices for illumination, entertainment, decoration or ornaments. | 10-25-2012 |
20120304713 | OPTICAL DEVICE - An optical device includes: a lock having a locking unit and an operation unit having at least a sensor; and a key configured to correspond to the lock. The key includes an unlocking unit having at least a light-guiding element for transmitting light between the operation unit and the unlocking unit. The operation unit is activated to unlock the locking unit after the sensor detects and recognizes the transmitted light. After encoding, the optical device of the present invention cannot be reproduced and the encoded light beam will not be intercepted and decoded easily so as to satisfy our security demands. Further, the structure of the optical device of the present invention does not decay easily. Therefore, the present invention has an excellent anti-theft effect and a reduced production cost. | 12-06-2012 |
20130299876 | Method For Improving Selectivity Of EPI Process - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 11-14-2013 |
20140017971 | Optical Toy - An optical toy is disclosed. The optical toy includes a frame, at least one emitting part, at least one receiving part, a plurality of light guiding parts, and at least one power source. The frame includes a container and at least one containing structure. The emitting part is movably located on the containing structure. The emitting part includes at least one light source for emitting light. The receiving part is movably located on the containing structure. The receiving part includes a light sensor for sensing the light. The plurality of light guiding parts is located in the container for changing the direction of the light. The relative positions of the plurality of light guiding parts can be changed. The power source is located in the frame for providing power to the optical toy. | 01-16-2014 |
20140085583 | DISPLAY PANEL - A display panel includes a pixel structure that has first, second, and third sub-pixels. In the first sub-pixel, a first pixel electrode having first branches and a second pixel electrode having second branches are alternately arranged. Gap dB is defined between adjacent first and second branches. In the second sub-pixel, a third pixel electrode having third branches and a fourth pixel electrode having fourth branches are alternately arranged. Gap dG is defined between adjacent third and fourth branches. In the third sub-pixel, a fifth pixel electrode having fifth branches and a sixth pixel electrode having sixth branches are alternately arranged. Gap dR is defined between adjacent fifth and sixth branches. The gaps dB, dG, and dR at least include minimum gaps dB | 03-27-2014 |
20140209978 | DEVICES WITH STRAINED SOURCE/DRAIN STRUCTURES - A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions. | 07-31-2014 |
20140308790 | METHODS FOR MANUFACTURING DEVICES WITH SOURCE/DRAIN STRUCTURES - In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material. | 10-16-2014 |
20140349544 | Illuminable Building block - An illuminable building block is disclosed. The illuminable building block has a cell body, at least one circuit board, at least one illuminating device, at least one photo sensing device, at least one circuit control module, and at least one assembly portion. The cell body has an accommodating space, and the circuit board is located therein. The at least one illuminating device is disposed at the inner surface of the circuit board, and each photo sensing device corresponds to at least one illuminating device. The at least one circuit control module is used for illuminating the illuminating device. | 11-27-2014 |