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| 20090125471 | Event detection and method and system - An event detection method is disclosed. At least one most adaptable life cycle model is generated according to at least one historical event data, at least one nutrition growing function, and at least one firing point rule. Event data is received and a strength value thereof is calculated according to a life cycle model corresponding to the event data. It is determined whether an event firing point is achieved according to the strength value variation. If the event firing point is achieved, an event corresponding to the event data is sent. The event detection method enhances the ability of event tracking and development so event firing is more accurate to fit real event occurring situations, realize event evolution, and filter false alarms. | 05-14-2009 |
| 20100214198 | DISPLAY DEVICE - A display device includes a display panel, a flexible printed circuit and a back light module. The flexible printed circuit is suitable for supporting the driving element and is electrically connected to the display panel. The back light module includes at least one light source, a first frame and a second frame. The light source is disposed between the first frame and the second frame, and the display panel and the flexible printed circuit are disposed at one side of the first frame, wherein the first frame has at least an opening, the second frame has a element contacting surface, the driving element is disposed on the flexible printed circuit, and the element contacting surface protrudes from the opening for being connected to the driving element. | 08-26-2010 |
| 20100214199 | DISPLAY DEVICE FOR PREVENTING ELECTROMAGNETIC INTERFERENCE - A display device includes a display panel, a back light module, a printed circuit board and a ground slice. The back light module includes a first frame, a second frame and a light source disposed between the first frame and the second frame. The first frame has a first side plate having an opening, and the second frame has a second side plate opposite to the first side plate. The printed circuit board includes a control circuit electrically connected to the display panel. The printed circuit board is disposed at a side of the back light module, and the control circuit is disposed at the outer side of the first side plate and the second side plate, such that the control circuit is opposite to the second side plate through the opening. The ground slice is connected between the control circuit and the second side plate through the opening. | 08-26-2010 |
| 20110079807 | LIGHT-EMITTING DIODE STRUCTURE - A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block. | 04-07-2011 |
| 20110119373 | SERVICE WORKFLOW GENERATION APPARATUS AND METHOD - A service workflow generation apparatus, having a quality of service (QoS) monitor for obtaining a plurality of real time QoS values respectively corresponding to a plurality of service elements on the web. A QoS calculation module generates a plurality of possible service workflows composed of the service elements and a plurality of overall QoS values of the possible service workflows based on the real time QoS values by using a Modified Heuristic Algorithm. A service workflow selection module dynamically selects a service workflow from the possible service workflows according to the overall QoS value. | 05-19-2011 |
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| 20080246057 | Silicon layer for stopping dislocation propagation - A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices. | 10-09-2008 |
| 20100127898 | INPUT APPARATUS, INPUT METHOD AND ELECTRONIC APPARATUS USING THE SAME - An input apparatus, an input method and an electronic apparatus are provided. The input apparatus includes a signal generating module and a processing module. The signal generating module generates a plurality of input signals by executing multi-direction operations. The processing module receives two signals of the input signals which are successively generated by the signal generating module, thus generating a control signal. The control signal corresponds to one of a plurality of characters. Therefore, the input apparatus can be more conveniently used by users to input characters by executing multi-direction operations. | 05-27-2010 |
| 20110073952 | Controlling the Shape of Source/Drain Regions in FinFETs - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. | 03-31-2011 |
| 20110199370 | Image Processing Method for Feature Retention and the System of the Same - The present invention discloses an image processing method for feature retention associated with averaging processes. The image processing method comprises: scaling and aligning a plurality of image data for acquiring feature information; determining a plurality of two-dimensional feature label points according to the feature information for generating at least one Bezier curve; utilizing the at least one Bezier curve to generate at least one Bezier tube and performing Bezier tube fitting for generating result of Bezier tube fitting; deforming the plurality of image data according to the Bezier tube or the result of Bezier tube fitting for generating a plurality of deformed image data; and averaging the plurality of deformed image data for generating feature-preserved average image data. The present invention also provides an image processing system, a computer readable storage medium, and a computer program product, for implementing the image processing method. | 08-18-2011 |
| 20110210404 | Epitaxy Profile Engineering for FinFETs - A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin. | 09-01-2011 |
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| 20100134234 | SHIFT REGISTER APPARATUS - A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof. | 06-03-2010 |
| 20110024801 | TRANSISTORS HAVING A COMPOSITE STRAIN STRUCTURE, INTEGRATED CIRCUITS, AND FABRICATION METHODS THEREOF - A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate. | 02-03-2011 |
| 20110042729 | METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 02-24-2011 |
| 20110108894 | METHOD OF FORMING STRAINED STRUCTURES IN SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material. | 05-12-2011 |
| 20110147846 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 06-23-2011 |
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| 20090134913 | SIGNAL COMPARISON CIRCUIT - A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison. | 05-28-2009 |
| 20090219056 | SIGNAL DETECTION CIRCUIT WITH DEGLITCH AND METHOD THEREOF - A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal. | 09-03-2009 |
| 20100060345 | REFERENCE CIRCUIT FOR PROVIDING PRECISION VOLTAGE AND PRECISION CURRENT - A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage. | 03-11-2010 |
| 20100073045 | FREQUENCY DETECTION CIRCUIT AND DETECTION METHOD FOR CLOCK DATA RECOVERY CIRCUIT - A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal. | 03-25-2010 |
