| Patent application number | Description | Published |
| 20080220547 | SINGLE-CHIP SURFACE MOUNTED LED STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A single-chip surface mounted LED structure and a method for manufacturing the same, said LED structure mainly comprises an LED chip, a heat sink structure, two opposing electrodes, conducting wires and a supporting structure; said method comprises the steps of firstly cutting off a spare area other than said heat sink structure and two opposing electrodes from a metal material belt, forming a basic shape, forming said supporting structure in the region of said heat sink structure and two opposing electrodes using plastic injection molding, and then further cutting off the rest of said metal material belt to separate said heat sink structure and two opposing electrodes, and finally using chip-bonding and wire bonding to package sad LED structure and cutting off said packaged LED structure from said metal material belt. | 09-11-2008 |
| 20080220548 | MULTI-CHIP SURFACE MOUNTED LED STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A multi-chip surface mounted LED structure and a method for manufacturing the same, said LED structure comprises a plurality of equivalent lighting units, each lighting unit comprises an LED chip, a heat sink structure, two opposing electrodes, said plurality of equivalent lighting units are mutually connected by a supporting structure; said method comprises the steps of firstly cutting a metal material belt to form a basic shape and using plastic injection molding to form said supporting structure, and then using chip bonding and wire bonding to connect said two opposing electrodes, and connecting adjacent lighting units in series/parallel, and finally cutting off a spare region of said metal material belt and packaging sad LED structure to form said multi-chip surface mounted LED structure; furthermore, a plurality of multi-chip surface mounted LED structures can be mutually connected in series/parallel by directly cutting said metal material belt to form a connection area thereon to enable conductivity between adjacent multi-chip surface mounted LED structures. | 09-11-2008 |
| Patent application number | Description | Published |
| 20090213656 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 08-27-2009 |
| 20090276737 | TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS - A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants. | 11-05-2009 |
| 20100120210 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 05-13-2010 |
| Patent application number | Description | Published |
| 20090138442 | System and method for generating 'snapshot's of learning objects - A system for generating a ‘snapshot’ of a learning object is provided. An interface receives a target object and a user identification number. The target object corresponds to a category, comprising a plurality of sentences and multimedia data, wherein the sentences comprise at least one keyword. A learning object database comprises a plurality of learning objects and a user's historical learning record. Each of the learning objects corresponds to at least one category, and comprises at least one keyword. The user's historical learning record comprises a track record of learning objects used corresponding to the user identification number. A script preview unit selects at least one of the sentences of the target object according to the user's historical learning record corresponding to the user identification number. A multimedia preview unit selects one of the multimedia data of the target object, wherein the selected multimedia data is highly related to the selected sentence. A ‘snapshot’ generator generates a ‘snapshot’ of the target object by combining the selected sentence and the selected multimedia data, and directs a display device to display the ‘snapshot’. | 05-28-2009 |
| 20100063798 | ERROR-DETECTING APPARATUS AND METHODS FOR A CHINESE ARTICLE - The invention discloses an error-detecting method for a Chinese article, handling a Chinese sentence including a first erroneous Chinese character string in a first location. The method includes subdividing the first erroneous Chinese character string into a plurality of first subgroups, wherein each of the first subgroups consists of two consecutive and non-consecutive Chinese characters out of the first erroneous Chinese character string. The method further includes providing a database containing a plurality of first correct Chinese character strings and a plurality of corresponding first correct indices, wherein the first correct indices consist of two consecutive and non-consecutive Chinese characters out of the first correct Chinese character strings. The method further includes acquiring one of the first correct indices according to the first subgroup, and one of the first correct Chinese character strings according to the acquired first correct index. The method further includes generating a best candidate sentence according to the acquired first correct Chinese character string, and showing the Chinese sentence and the best candidate sentence on a display device. | 03-11-2010 |
| 20100138217 | METHOD FOR CONSTRUCTING CHINESE DICTIONARY AND APPARATUS AND STORAGE MEDIA USING THE SAME - A method for constructing a Chinese dictionary is disclosed, including determining a probability for nominalization of a Chinese term with a given collocation term according to a determination rule and the correlation between the Chinese term and its corresponding collocations, wherein the Chinese term is determined to be a verb part-of-speech. The method further includes modifying the verb part-of-speech of the Chinese term with the given collocation term to an appropriate part-of-speech when the probability for nominalization of the Chinese term with the given collocation term is higher than a predetermined value, and storing the correlation between the Chinese term, the given collocation term and the appropriate part-of-speech in a storage device. | 06-03-2010 |
| 20110087481 | TRANSLATION SYSTEM, TRANSLATION METHOD AND COMPUTER READABLE-WRITABLE STORAGE MEDIUM OF THE SAME - A translation system is provided. The system includes an input interface for receiving a term to be translated, a multi-language term processing module, a term correlation calculation module and an analysis module. The multi-language term processing module collects multi-language correlated terms corresponding to the term to be translated and language data sources, and establishes term pairs each including any two multi-language correlated terms having a relationship in translation. The multi-language correlated terms include at least the term to be translated and at least one candidate translated term in the target language. The term correlation calculation module calculates a term correlation value between the two multi-language correlated terms of each term pair and a self correlation value of each multi-language correlated term. The analysis module determines one of the candidate translated terms as the translation result term according to the term correlation values and the self correlation values. | 04-14-2011 |
| 20110258194 | NAMED ENTITY MARKING APPARATUS, NAMED ENTITY MARKING METHOD, AND COMPUTER READABLE MEDIUM THEREOF - A named entity marking apparatus, a named entity marking method, and a computer program product thereof are provided. The named entity marking apparatus comprises a processor and a storage unit, wherein the processor is electrically connected to the storage unit. The storage unit is stored with an electronic document and a named entity database. The processor marks the electronic document into a first marked document by a first set of the named entity database. The processor decides a second set of the named entity database according to the first marked document. The processor re-marks the electronic document into a second marked document by the second set of the named entity database. | 10-20-2011 |
| Patent application number | Description | Published |
| 20090302943 | CLASS D AMPLIFIER - A class D amplifier including a PWM circuit, a buffer amplifying circuit, a low-pass filter, and two current sources is provided. The PWM circuit transfers an analog signal into a PWM signal. The buffer amplifying circuit amplifies the PMW signal and generates an amplified signal. The low-pass filter will filter high frequency components out from the amplified signal and then transmit the filtered signal to a loading of the class D amplifier. The two current sources provide currents flowing into and out from a feedback node in the PWM circuit, respectively. The charging and discharging provided by the two current sources can generate a triangular signal for the PWM circuit. | 12-10-2009 |
| 20100253427 | CLASS-D AMPLIFIER - The invention discloses a class-D amplifier, which is used for driving a two-terminal load according to a set of analog signals. The D-class amplifier includes a pulse-width modulation (PWM) circuit, a signal processing circuit and a driving amplifier circuit. The PWM circuit receives the set of analog signals and converts them into a set of PWM signals with identical phase. The signal processing circuit generates a set of pulse signals which are attached to the set of PWM signals respectively. The driving amplifier circuit is coupled between the signal processing circuit and the two-terminal load. The driving amplifier circuit receives and amplifies the set of PWM signals. According to the set of PWM signals, the driving amplification circuit drives the two-terminal in a filterless way. | 10-07-2010 |
| 20110110539 | SELF-OSCILLATING AUDIO AMPLIFIER AND METHOD FOR RESTRAINING THE IMPROVED SELF-OSCILLATING AUDIO AMPLIFIER - An improved self-oscillating audio amplifier and a method for restraining audio distortion of the self-oscillating audio amplifier are disclosed. The improved self-oscillating audio amplifier comprises a distortion restraint unit configured to detect whether modulated audio signals outputted from the self-oscillating audio amplifier is distorted and, if so, to restrain the distortion. The method for restraining audio distortion of the self-oscillating audio amplifier includes the following steps of: determining whether the modulated audio signals outputted from an audio amplifier positive output terminal is distorted by a first flip-flop set, and if yes, restraining the distortion of the modulated audio signals outputted from the audio amplifier positive output terminal; and outputting the modulated audio signals to drive a speaker by the audio amplifier positive output terminal and an audio amplifier negative output terminal. | 05-12-2011 |