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Ku, Hsinchu
Hao-Min Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100143657 | HIGH-TEMPERATURE-DURABLE OPTICAL FILM STRUCTURE AND FABRICATION METHOD THEREOF - A high-temperature-durable optical film structure and its fabricating method are provided. The optical film structure is formed by covering a surface of a substrate with an optical layer structure and forming a plurality of passage structures on the optical layer structure to divide the optical layer structure into a plurality of optical blocks. The passage structures can be used as a space of releasing the thermal stress to prevent the film deformation and peeling. | 06-10-2010 |
| 20100148148 | FABRICATION METHOD OF A LIGHT-EMITTING ELEMENT AND THE LIGHT-EMITTING ELEMENT - A fabrication method of the light emitting element and its light emitting element are disclosed herein. It utilizes the membrane forming technology to form optic films arranged in array on a substrate and then upward forming the epitaxial layer by the epitaxial lateral overgrowth (ELOG) technology so as to form light-emitting elements in array. The optic films contribute to the high reflection property and can sustain high temperature in the ELOG process. | 06-17-2010 |
| 20100203245 | FABRICATION METHOD OF A PHOTONIC CRYSTAL STRUCTURE - A method for fabricating a photonic crystal structure is disclosed herein for forming a cavity-type or a pillar type photonic crystal structure of a large area. By the property that a hetero-interface inhibits epitaxial growth, a patterned film layer is formed over the epitaxy substrate, so a photonic crystal structure is grown vertically by epitaxy in area outside of the patterned film layer on the epitaxy substrate. Furthermore, by designing the pattern of the patterned film, a defect mode photonic crystal structure such as an optical waveguide, an optical resonator and a beam splitter can be formed. | 08-12-2010 |
Hui-Ling Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090152552 | PIXEL STRUCTURE AND REPAIRING METHOD THEREOF - A pixel structure disposed on a substrate and including a common line, a reserved line, a dielectric layer, two repair lines, an active device, and a pixel electrode is provided. The reserved line and the common line are disposed on the substrate and are covered by the dielectric layer. The repair lines are disposed on the dielectric layer, and each repair line has a first repairing region overlapped with the common line and a second repairing region overlapped with the reserved line. When the common line is open, the repair lines in the first and second repairing regions are connected with the common line and the reserved line, such that the common line, the repair lines, and the reserved line are electrically connected. After the common line, the repair lines, and the reserved line are connected, the above-mentioned pixel structure is effectively repaired. | 06-18-2009 |
Kai-Ning Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120008896 | INTEGRATED OPTICS MODULE FOR MULTIPLEX TRANSCEVIER - The present invention relates to an integrate optics for multiplexer transceiver module, comprising: a substrate, a multiplexer, a first waveguide coupling device, a second waveguide coupling device and a third waveguide coupling device. In the present invention, the semiconductor materials and the semiconductor process are used to integrate variety of optical devices on a single semiconductor substrate (chip) by way of modular design and miniaturization, so as to carry out an integrated optics communication framework with high efficiency and low cost. Moreover, in the present invention, a plurality of optical receivers are integrated on the substrate by means of flip-chip bonding, so that, not only the objective of integrating the optical devices is accomplished but also the intensity of laser optical signal is increased. | 01-12-2012 |
Shaw-Hung Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090091983 | NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF - A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively. | 04-09-2009 |
Yao-Ching Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110230998 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
| 20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
Yi-Sha Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080217794 | Overlay Measurement Target - In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy. | 09-11-2008 |
Yi-Wen Ku, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090140280 | Light-emitting device - A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of side surface of the epitaxial structure and a part of surface of the first semiconductor layer, so that a first conductive structure is formed on the part of surface of the first semiconductor layer in the trench, and a second conductive structure is formed on the second semiconductor layer. The first conductive structure includes a first electrode and a first pad electrically contacted with each other. The second conductive structure includes a second electrode and a second pad electrically contacted with each other. Furthermore, the area of at least one of the first pad and the second pad is between 1.5×10 | 06-04-2009 |