Patent application number | Description | Published |
20090296791 | Multi-Pair Gigabit Ethernet Transceiver - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 12-03-2009 |
20100309963 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING ADAPTIVE DISABLING OF CIRCUIT ELEMENTS - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 12-09-2010 |
20110064123 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 03-17-2011 |
20110096824 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 04-28-2011 |
Patent application number | Description | Published |
20110192240 | SLED TEST APPARATUS - A sled test apparatus for simulating a vehicle crash is configured to simulate a vehicle crash involving an intrusion into the cabin of the vehicle, as occurs, for example, in a so-called “small overlap” or “offset” impact. The apparatus has a sled carriage and a test buck. The sled carriage is mounted for linear movement along a test axis, and the test buck includes a first structure mounted to the carriage for guided movement relative to the carriage. The test buck further includes a second structure mounted to the carriage, and the first structure is configured to move relative to the second structure during the guided movement. | 08-11-2011 |
20130270805 | CURTAIN AIRBAG FOR A VEHICLE - A curtain airbag for a vehicle includes a main chamber shaped in such a way that, in a position being mounted on the vehicle, in the inflated state the main chamber covers an inner side structure of the vehicle. The curtain airbag further includes an additional chamber which, in the mounting position, is located on the in driving direction of the vehicle front portion of the main chamber, and deploys in the direction of the interior of the vehicle when the curtain airbag is inflated. | 10-17-2013 |
20150115581 | CURTAIN AIRBAG FOR A VEHICLE - A curtain airbag for a vehicle includes a main chamber shaped in such a way that, in the position being mounted on the vehicle, in the inflated state the main chamber covers an inner side structure of the vehicle. The curtain airbag further includes an additional chamber which, in the mounting position, is located on the in driving direction of the vehicle front portion of the main chamber, and deploys in the direction of the interior of the vehicle when the curtain airbag is inflated. An extended section connects the additional chamber and the main chamber at a rim section at the same side and limits movement of the additional chamber during the inflation process. | 04-30-2015 |
Patent application number | Description | Published |
20090239756 | PREDICTORS FOR METASTASIS OF BREAST CANCER - There is provided a gene expression pattern which is clinically relevant to metastasizing breast cancer. In particular, the identity of genes that are correlated with patient survival and breast cancer recurrence are provided. The gene expression profile, whether embodied in nucleic acid expression, protein expression, or other expression formats, may be used to predict survival of subjects afflicted with breast cancer and the likelihood of breast cancer recurrence. The invention thus provides for the use of a gene expression pattern (or profile or “signature”) which correlates with (and thus able to discriminate between) patients with good or poor survival outcomes. | 09-24-2009 |
20090297563 | Diagnosis And Treatment of Immune-Related Diseases - The present invention relates to association of one or more polymorphisms located in the human SFRS8, CD83, SLAMF1, CD86, HRH1, IL2, TLR7, TLR8 and TLR10 genes to the occurrence of allergic diseases such as rhinitis, asthma, and atopic dermatitis, auto-immune diseases, infectious diseases, and graft/host incompatibilities. The invention relates both to methods for diagnosing a predisposition to said diseases, classifying said diseases and to methods and compositions for treating subjects with said diseases. Furthermore the invention relates to screens for identifying compounds effective in treating said diseases. The invention describes specific single nucleotide polymorphisms the presence of which in the genome of an individual is strongly associated with the predisposition of said individual to an immune related disease. | 12-03-2009 |