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Kruger, CA
Matt S. Kruger, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120126935 | BRIDGE BETWEEN SECURITY SYSTEM AND APPLIANCES - A method and apparatus for controlling an appliance. The method includes the steps of a security system within a secured area, said security system having a wireless transmitter transmitting status messages including at least a first encrypted message that the security system in armed and a second encrypted message that the security system is disarmed, an appliance control device having a wireless receiver and a decryption unit, the wireless receiver receiving the first and second encrypted messages, the decryption unit decrypting the first encrypted message to recover the armed status message and decrypting the second encrypted message to recover the disarmed status message and an appliance associated with the secured area and controlled by the appliance control device, the appliance entering a relatively low energy consuming mode in response to the appliance control device receiving the armed message and the appliance entering a relatively high energy consuming mode in response to the appliance control device receiving the disarmed message. | 05-24-2012 |
Michiel Victor Paul Kruger, Berkeley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090307649 | SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK - The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer. | 12-10-2009 |
Michiel V.p. Kruger, Berkeley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090292506 | METHODS OF AND APPARATUSES FOR MAINTENANCE, DIAGNOSIS, AND OPTIMIZATION OF PROCESSES - One aspect of the present invention is a method of monitoring processes, optimizing processes, and diagnosing problems in the performance of a process tool for processing a workpiece. Another aspect of the present invention is a system configured for monitoring processes, optimizing processes, and diagnosing problems in the performance of a process tool for processing a workpiece. One embodiment of the present invention includes a software program that can be implemented in a computer for optimizing the performance of a process tool for processing a workpiece. | 11-26-2009 |
Torsten Kruger, Oceanside, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090175686 | Fluid injection deflector shield viewing apparatus and method - A fluid injection deflector shield viewing apparatus with a deflector shield, a fluid concentrating focal area on one side of the deflector shield, an anchoring means to secure the deflector shield in the desired location, a fluidic material of decreased visibility, an observation means, a filtration system to filter the fluidic material, an intake to take in the fluidic material of decreased visibility, a discharge for introducing the filtered fluidic material into the fluid concentrating focal area on one side of the deflector shield, and a fluid transport means to transport the filtered fluidic material to the discharge. A preferred embodiment includes having a moving anchoring system so as to change the position of the deflector shield. A preferred embodiment includes a means for moving the anchoring system so as to change the position of the deflector shield comprised of a plurality of self propelled thrusters. | 07-09-2009 |
Tracey Kruger, Valencia, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120029595 | Bilateral Sound Processor Systems and Methods - An exemplary sound processor includes a storage facility configured to maintain data representative of a first program set associated with a first cochlear implant and data representative of a second program set associated with a second cochlear implant, a detection facility configured to detect when the sound processor is communicatively coupled to the first cochlear implant and to detect when the sound processor is communicatively coupled to the second cochlear implant, and an operation facility configured to operate in accordance with the first program set in response to a detection that the sound processor is communicatively coupled to the first cochlear implant and to operate in accordance with the second program set in response to a detection that the sound processor is communicatively coupled to the second cochlear implant. Corresponding methods and systems are also described. | 02-02-2012 |
Warren Kruger, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090313323 | Method and System for Controlling Bus Access - A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same. | 12-17-2009 |
Warren F. Kruger, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090300278 | Embedded Programmable Component for Memory Device Training - A system and method by which a memory device can adapt or retrain itself in response to changes in its inputs or operating environment. The memory device, such as a DRAM, includes in its interface an embedded programmable component. The programmable component can be, for example and without limitation, a microprocessor, a microcontroller, or a microsequencer. A programmable component is programmed to make changes to the operation of the interface of the memory device, in response to changes in the environment of the memory device. | 12-03-2009 |
| 20110093644 | Memory Controller With Ring Bus for Interconnecting Memory Clients to Memory Devices - Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic. | 04-21-2011 |
Warren Fritz Kruger, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090147015 | Aperture Compression for Multiple Data Streams - A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request. | 06-11-2009 |
| 20090248941 | Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus. | 10-01-2009 |
| 20100329045 | Adjustment of Write Timing in a Memory Device - A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal. | 12-30-2010 |
| 20110019787 | Method and Apparatus Synchronizing Integrated Circuit Clocks - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 01-27-2011 |
| 20110060879 | SYSTEMS AND METHODS FOR PROCESSING MEMORY REQUESTS - A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit. | 03-10-2011 |
| 20110148923 | POWER EFFICIENT MEMORY - A circuit includes a memory circuit. The memory retiling circuit moves image information configured to be distributed among a plurality of memory channels into reconfigured image information configured to be distributed among a subset of the plurality of memory channels. | 06-23-2011 |
| 20110185218 | Adjustment of Write Timing Based on a Training Signal - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
| 20110185256 | Adjustment of Write Timing Based on Error Detection Techniques - A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
| 20110208989 | Command Protocol for Adjustment of Write Timing Delay - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal. | 08-25-2011 |
W. Fritz Kruger, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120066471 | ALLOCATION OF MEMORY BUFFERS BASED ON PREFERRED MEMORY PERFORMANCE - A method and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method and apparatus associates one or more memory buffers with a plurality of memory banks based on preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels. Additionally, the method and apparatus accesses the one or more memory buffers based on the preferred performance settings. Further, the method and apparatus can, in response to accessing the one or more memory buffers based on the preferred performance settings, determine whether the preferred performance settings are being satisfied. | 03-15-2012 |