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Kroener, DE
Christine Kroener, Worms-Pfeddersheim DE
| Patent application number | Description | Published |
|---|---|---|
| 20110250534 | SOLUBILIZER FOR METAL IONS - The invention relates to solubilizers for metal ions and poorly soluble metal compounds, containing an oxidation product of starch hydrolysate as a solubilizing agent, to a method for solubilizing metal ions and to the use of said solubilizer. | 10-13-2011 |
Gregor Kroener, Bischberg DE
| Patent application number | Description | Published |
|---|---|---|
| 20100222174 | WOBBLE MECHANISM - A wobble mechanism, in particular for a two-part adjustment fitting of a vehicle seat, is provided with a flat housing with internal toothing and with an oscillating wheel with external toothing, which is arranged within the housing and is eccentrically rotatable around a center axis of the housing. The external toothing of the oscillating wheel engages with the internal toothing of the housing. The housing is divided into at least two housing parts along a dividing plane. | 09-02-2010 |
| 20100295349 | METHOD FOR AUTOMATICALLY ADJUSTING A HEADREST OF A MOTOR VEHICLE SEAT, AND DEVICE FOR CARRYING OUT SAID METHOD - A method for automatically adjusting a headrest of a motor vehicle seat, which can individually be adjusted to a passenger occupying the motor vehicle seat with a sensor array and an electronically controlled adjusting device such that the headrest is in an adjusted position which is defined as optimal as possible for absorbing acceleration forces acting on the head of the passenger in a case of crash is provided. The adjusting device can be controlled via a control unit which evaluates at least one signal of at least one sensor, in order to control the adjustment of the headrest with the adjusting mean. At least one signal from the at least one sensor serves to detect an occupation of the motor vehicle seat by a passenger. | 11-25-2010 |
| 20110062737 | MOTOR VEHICLE REAR SEAT - A rear seat for a motor vehicle with a seat part and a backrest which is upright in a seating position and folded down in a loading position, and in the loading position increases the loading space floor with its rear side facing a loading space of the motor vehicle is provided. The seat part is connected with at least one electromotive drive for translatorily adjusting and/or folding down the seat part from the seating position into the loading position and for translatorily returning and/or folding back the seat part from the loading position into the seating position. | 03-17-2011 |
| 20110278892 | VEHICLE SEAT COMPRISING A PLURALITY OF STRUCTURAL OR RETAINING PARTS AS WELL AS A METHOD FOR PRODUCING STRUCTURAL OR RETAINING PARTS OF SUCH A VEHICLE SEAT - The invention relates to a vehicle seat and to a method for producing said vehicle seat, in particular for motor vehicles, comprising a plurality of structural or retaining parts which are joined together or to a further part in at least one joining region, the join being produced by friction welding in at least one of the joining regions. | 11-17-2011 |
Hans Kroener, Geislingen-Weiler DE
| Patent application number | Description | Published |
|---|---|---|
| 20090052431 | METHOD AND DEVICE FOR PACKET BASED CLOCK RECOVERY - A master clock in a first radio network unit, configured for sending data packets at predetermined time intervals, is synchronized with a slave clock in a second radio network unit. To provide a method for packet based clock recovery being able to achieve the desired accuracy within an acceptable time while avoiding a high computational complexity, the following procedure is used. An estimate value is determined for the transmission delay time for each data packet in a predetermined set of data packets. At least one pair of data packets is selected that has a minimum estimate value for the transmission delay time. A difference of the reception times of the selected pair of data packets is determined. Finally, a clock estimate procedure is performed using the difference of the reception times of the selected pair of data packets to determine the quantity representative of the clock frequency difference and/or the clock time offset. | 02-26-2009 |
Klaus M. Kroener, Ehningen DE
| Patent application number | Description | Published |
|---|---|---|
| 20110320514 | DECIMAL ADDER WITH END AROUND CARRY - Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps. | 12-29-2011 |
K. Michael Kroener, Ehningen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100063987 | SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR - In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit. | 03-11-2010 |
Michael Kroener, Braunschweig DE
| Patent application number | Description | Published |
|---|---|---|
| 20090165846 | TRIPLET EMITTER HAVING CONDENSED FIVE-MEMBERED RINGS - The present invention relates to light emitting compounds, especially to triplett emitters suitable for electrooptical applications. Compounds according to the invention are organometallic complexes of a metal, preferably Ir, having a backbone of one five-membered ring that is linked to a five- or six-membered ring, by an intermediate six-membered ring. These compounds are suitable for adaptation to the emission of light in the UV to NIR range by adaptation of atoms or groups within at least one of the five-membered or six-membered ring structures. | 07-02-2009 |
Michael Kroener, Ehningen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100058266 | 3-Stack Floorplan for Floating Point Unit - A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer. | 03-04-2010 |
| 20100095099 | SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS IN A REGISTER FILE - A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers. | 04-15-2010 |
| 20100100713 | FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES - A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail. | 04-22-2010 |
| 20110320512 | Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection - A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format. | 12-29-2011 |
Michael K. Kroener, Ehningen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100146027 | RESIDUE CALCULATION WITH BUILT-IN CORRECTION IN A FLOATING POINT UNIT - A residue generator for calculation and correction of a residue value. The residue generator includes a residue-generation tree connected with an operand register at an input of the residue generator including a plurality of register-bits receiving and carrying bits of numerical data. The residue-generation tree includes a multiplexer connected with respective register-bits which carry unused bits, and selectively providing logical zeros or a correction value when provided, at the respective register-bits carrying the unused bits, a plurality of decoders, each decoder receiving the bits of numerical data from the respective registers-bits including the logical zeros or the correction value when provided and decoding the numerical data, and a plurality of residue condensers, receiving the decoded numerical data from the decoders including the logical zeros or the correction value when provided, and calculating the residue value and correcting while calculating the residue value using the correction value when provided by the multiplexer. | 06-10-2010 |
Michael Klaus Kroener, Ehningen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100100578 | DISTRIBUTED RESIDUE-CHECKING OF A FLOATING POINT UNIT - A distributed residue checking apparatus for a floating point unit having a plurality of functional elements performing floating-point operations on a plurality of operands. The distributed residue checking apparatus includes a plurality of residue generators which generate residue values for the operands and the functional elements, and a plurality of residue checking units distributed throughout the floating point unit. Each residue checking unit receives a first residue value and a second residue value from respective residue generators and compares the first residue value to the second residue value to determine whether an error has occurred in a floating-point operation performed by a respective functional element. | 04-22-2010 |
Thilo Kroener, Kerpen DE
| Patent application number | Description | Published |
|---|---|---|
| 20090010708 | PRESTRESSED SHAFT AND HUB CONNECTION HAVING A PERFECT CONE SHAPE - The invention relates to a shaft and hub connection ( | 01-08-2009 |