Patent application number | Description | Published |
20080263332 | Data Processing Apparatus and Method for Accelerating Execution Subgraphs - A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs. | 10-23-2008 |
20090049331 | Error propagation control within integrated circuits - A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation. | 02-19-2009 |
20090213673 | Data processor memory circuit - A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state. | 08-27-2009 |
20140181581 | ERROR RECOVERY WITHIN INTEGRATED CIRCUIT - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 06-26-2014 |
20140372762 | TRUSTED DEVICE - A trusted device, such as a wristwatch | 12-18-2014 |
20150048926 | Interacting with embedded devices within a user's environment - An envoy device configured to perform a transaction with a further device. The envoy device comprises: a data store; a processor; communication circuitry for communicating with the further device; and a display. The envoy device is configured to respond to detection of the further device being within a predetermined physical proximity to trigger initiation of a transaction between the devices; and to respond to the transaction completing to display an object related to the transaction that it is determined the user may wish to select to initiate a subsequent action. | 02-19-2015 |
20150050885 | Establishing communication links automatically with local devices - An envoy device for performing transactions with a further device in proximity to the envoy device, the envoy device comprising: a first communication device configured to communicate with the further device that is located within a predetermined distance of the envoy device using a local short range communication link; at least one further communication device configured to communicate with the further device using at least one longer range communication link. The envoy device is configured to respond to detecting the further device within the predetermined distance of the envoy device to: establish communication with the further device using the local short range communication link; receive information from the further device regarding any further communication links that the further device has access to; transmit to the further device information regarding the at least one longer range communication link; and to commence a transaction with the further device using the local short range communication link. | 02-19-2015 |
20150052066 | RECONCILING ELECTRONIC TRANSACTIONS - An apparatus, system and method for establishing a transaction between first and second parties including a first signing step in which a transaction message including a request and a transaction identifier is cryptographically signed by the first party to form a first cryptographically signed message. The first signed message is transmitted from the first party to the second party. The second party then cryptographically signs the first message to form a second cryptographically signed message. The second message is also transmitted from one or more of a plurality of parties having the second message to a trusted third party. The trusted third party is able to verify that the second message was cryptographically signed by the second party and can also verify that the first message in the second message was cryptographically signed by the first party. | 02-19-2015 |