Krishnappa
Bhavya Krishnappa, Bangalore IN
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20120116592 | PROGRAMMABLE HVAC CONTROLLER WITH CROSS COLUMN SELECTION ON A TOUCH SCREEN INTERFACE - A programmable HVAC controller that include a controller and a touch screen user interface is configured to control one or more pieces of HVAC equipment in accordance with a programmable schedule. In some instances, the controller of the programmable HVAC controller is programmed to define a number of columns on the touch screen display, such that a selected day of the programmable schedule may be visually represented across two or more adjacent columns of the touch screen display, with the selected day of the programmable schedule beginning in a first column and extending across and into a second adjacent column of the touch screen display. The controller may be programmed to monitor the touch screen display and allow a user to set a start time and/or an end time of a time period of the selected day of the programmable schedule by touching the first column and/or the second column of the touch screen display. | 05-10-2012 |
Chandrashekar Krishnappa, Lucknow IN
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20150139976 | NOVEL INSECTICIDAL CHITINASE PROTEIN ITS ENCODING NUCLEOTIDE AND APPLICATION THEREOF - A novel insecticidal chitinase protein from fern | 05-21-2015 |
Chandrashekar Krishnappa, Luchnow IN
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20150073126 | ALLIUM FISTULOSUM LEAF AGGLUTININ RECOMBINANT PROTEIN, ITS ENCODING POLYNUCLEOTIDE, PRIMER AND PROCESS FOR PREPARATION THEREOF - Nucleic acid sequence encoding | 03-12-2015 |
Chinmayi Krishnappa, Austin, TX US
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20110270702 | DYNAMIC UNIT-DEMAND AUCTION - Systems and methods provide for a dynamic unit-demand auction that can support bid revision. Preparation of a unit-demand bid can involve specifying offers for multiple items, thus a unit-demand agent can intend to modify one or more components of an active bid. Embodiments of the system and methods provide a comprehensive solution to unit-demand bid revision problem including satisfying strong theoretical properties related to efficiency, truthfulness, privacy preservation, and scalability, and permitting various degrees of time performance. | 11-03-2011 |
Gopi Krishnappa, Chennai IN
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20140180949 | SYSTEM AND METHOD FOR AUTOMATED CODING AND TESTING OF BENEFITS - A system and method for automated coding and testing of insurance benefits is provided. The system comprises a user interface to receive data pertaining to benefits based on insurance benefits contracts and to create Benefit Plan Designs (BPDs) using the received data. The system further comprises a benefits mapping module to map the benefits from the BPDs with pre-stored benefits in a repository. Further, the system comprises a benefit code translator to translate the mapped benefits into codes or mnemonics and a benefit code updating engine to update the codes or mnemonics into one or more claims platforms. In addition, the system comprises a test scenario mapping module to generate test claims and expected results and to execute the generated test claims on the one or more claims platforms to generate actual test results. The system also comprises a validation engine to validate the codes or mnemonics. | 06-26-2014 |
Madan Krishnappa, San Diego, CA US
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20140157007 | SYSTEM AND METHOD OF ADAPTIVE VOLTAGE SCALING - A particular method includes, prior to issuing a recommendation by an adaptive voltage scaling (AVS) system, performing a first iteration of an AVS operation to sample characteristics of a semiconductor device to determine a first adjustment recommendation. The method further includes performing at least one additional iteration of the AVS operation to determine at least one additional adjustment iteration. When a threshold number of consecutive adjustment recommendations are consistent, the method includes issuing the recommendation by the AVS system. | 06-05-2014 |
20140191794 | METHOD FOR PERFORMING ADAPTIVE VOLTAGE SCALING (AVS) AND INTEGRATED CIRCUIT CONFIGURED TO PERFORM AVS - An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided. | 07-10-2014 |
20140232188 | METHOD AND APPARATUS FOR HYBRID CHIP-LEVEL VOLTAGE SCALING - Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level | 08-21-2014 |
20160091939 | TOKEN-BASED POWER-SWITCH CONTROL CIRCUITS - A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring. | 03-31-2016 |
Mukunda Krishnappa, Cupertino, CA US
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20090072856 | MEMORY CONTROLLER FOR HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUITS - A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit. | 03-19-2009 |
20090072858 | HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT - A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system. | 03-19-2009 |
20090077308 | RECONFIGURABLE CONTENT-ADDRESSABLE MEMORY - A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM). | 03-19-2009 |
20150269300 | Memory Controller for Heterogeneous Configurable Integrated Circuit - A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit. | 09-24-2015 |
Nagendra Krishnappa, Bangalore IN
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20090113034 | Method And System For Clustering - A system and a method for automatic cluster formation by automatically selecting nodes based on a selection criteria configured by the user is disclosed. During a cluster re-formation process, a failed node may automatically get replaced by one of the healthy nodes in its network, which is not part of any cluster avoiding cluster failures. In case of a cluster getting reduced to a single node due to node failures and failed nodes could not be replaced due to non-availability of free nodes, the single node cluster may be merged with a existing healthy clusters in the network providing a constant level of high availability. The proposed method may also provide an affective load balancing by maintaining a constant number of member nodes in a cluster by automatically replacing the dead nodes with a healthy node. | 04-30-2009 |
20090265449 | Method of Computer Clustering - A method for clustering comprising acquiring the required number of nodes for cluster formation based on node selection criteria; electing a cluster coordinator; and assigning the packages on the member nodes. The cluster coordinator is elected based on the mean time between failures value of the member nodes which may be calculated with the help of a diagnostic tool by logging the failure instances of the member nodes. | 10-22-2009 |
Narayana Venkata Chalapathy Krishnappa, Gulper Kolar IN
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20140177883 | Total Angle 360-Angled Loudspeaker Cabinet Enclosure Designing Technology - The present invention provides angled loudspeaker cabinet enclosures utilized for sound reproduction. The invention mainly comprises a setup of loudspeaker cabinet enclosures which include front, centre and rear loudspeaker cabinet enclosure in various embodiments wherein the font surfaces of the speaker units are inclined to wherein the sound waves emanating from the speaker units directly reach the listener present at the direction of inclination of the front surface to provide clear, immersive and 360 degree angle coverage to the listener irrespective of the location of the listener with respect to the sound source by distributing sound waves uniformly across the listening area. | 06-26-2014 |
Pradeep Krishnappa, Kammardi IN
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20160055043 | PATTERN ANALYSIS FOR TRIAGING MEMORY LEAKS - A method of analyzing out-of-memory errors may include receiving a memory dump generated in response to an out-of-memory error, receiving an identification of an object class in the memory dump as a leak suspect that may be responsible for the out-of-memory error, matching the leak suspect with an analysis pattern specific to the object class, and extracting usage information from the memory dump using the analysis pattern. | 02-25-2016 |
Pradeep Kumar Sindhagatta Krishnappa, Bangalore IN
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20120209860 | EVENT SCHEDULING DEVICE AND METHOD - A method and device are provided for scheduling an event. Text is detected in a text application of a computing device. The detected text includes at least one keyword from one or more types of keyword. At least one event associated with a user of the computing device to be scheduled based on the detected text is determined. The at least one event is automatically scheduled based on the detected text. | 08-16-2012 |
Rajendra Prasad Krishnappa, Bangalore IN
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20150028624 | VEHICLE HOOD ASSEMBLY - A vehicle hood assembly includes a first panel member, a second panel member, and a third panel member disposed between the first panel member and the second panel member. The third panel member includes a corrugated body. The third panel member defines a plurality of panel perforations extending through the corrugated body in order to attenuate kinetic energy imparted to the hood assembly. | 01-29-2015 |
Shashikumar Mandya Krishnappa, Bangalore IN
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20140298328 | METHOD FOR ACTIVATING PROCESSOR CORES WITHIN A COMPUTER SYSTEM - A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks. | 10-02-2014 |
20140298345 | METHOD FOR ACTIVATING PROCESSOR CORES WITHIN A COMPUTER SYSTEM - A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks. | 10-02-2014 |
Yathin Krishnappa, San Jose, CA US
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20090177744 | Identifying and employing social network relationships - Methods and apparatus are described for detecting social relationships across multiple networks and/or communication channels. These social relationships may then be utilized in a wide variety of ways to support and enhance a broad range of user services. | 07-09-2009 |