Patent application number | Description | Published |
20090086588 | Timing extractor, and information playback apparatus and dvd device using the timing extractor - In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section | 04-02-2009 |
20090315878 | PHASE COMPARATOR, AND CLOCK GENERATION CIRCUIT, IMAGE DISPLAY DEVICE, AND REPRODUCTION SIGNAL PROCESSOR EACH USING THE SAME - In a synchronous reproduction signal processor, when a phase error between reproduction data and a clock is repeatedly detected such that a clock synchronized with a reproduction signal is generated based on the phase error, a filtering process unit ( | 12-24-2009 |
20100020250 | REPRODUCED SIGNAL PROCESSOR AND VIDEO DISPLAY - In a feedforward control type reproduced signal processor, a clock generator | 01-28-2010 |
20110043693 | SYNCHRONOUS CONTROL CIRCUIT AND VIDEO DISPLAY DEVICE - A synchronization control circuit is provided with a first sampling means for sampling the envelope signal of the modulation signal at a first sampling timing, a second sampling means for sampling the envelope signal at a second sampling timing, a third sampling means for sampling the envelope signal at a third sampling timing, a phase error calculation means for calculating a phase error value indicating the amount of synchronization deviation between the modulation signal and the reference clock signal using the outputs of the first, second, and third sampling means, a delay control means for generating a delay control signal on the basis of the phase error value, and a delay generation means for generating the first, second, and third sampling timing by delaying the reference clock signal based on the delay control signal. Thereby, a synchronization control circuit that can reduce the circuit size required for obtaining the synchronization with relative to the Early/Late system can be provided. | 02-24-2011 |
20110095786 | PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE - In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section | 04-28-2011 |
20110164675 | DIGITAL PLL CIRCUIT AND COMMUNICATION DEVICE - In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock. | 07-07-2011 |
20110205444 | RECEIVER, SIGNAL PROCESSING APPARATUS, AND VIDEO DISPLAY APPARATUS - A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock. | 08-25-2011 |
20110206144 | RECEIVER AND TRANSMISSION/RECEPTION SYSTEM - In a wireless receiver, a “variance” of an intermediate output signal of a demodulation section is calculated by a variance calculation section, and the calculated variance is used as a signal quality indicator which indicates the degree of goodness of a receiving condition. For example, when the “variance” is small, a gain of a low-noise amplifier is reduced, or an operation clock frequency of a baseband oscillator is reduced, etc. Thus, when the receiving condition indicated by the indicator is good and sufficient performance is ensured, the performance can be slightly lowered to reduce power consumption. The “variance” is a compact indicator which can be calculated using a simple operation, and is used as a new signal quality indicator. | 08-25-2011 |
20120007668 | FILTER CIRCUIT, TRANSMISSION FILTER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, COMMUNICATION APPARATUS, AND TIMING ADJUSTMENT METHOD FOR FILTER CIRCUIT - A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz. | 01-12-2012 |
20120081339 | DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS - In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit. | 04-05-2012 |
20130148758 | FILTER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, COMMUNICATION APPARATUS, SEMICONDUCTOR DEVICE, AND SYSTEM - A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz. | 06-13-2013 |
20130285579 | ACTUATOR DRIVER - A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ΔΣ A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ΔΣ A/D converters to feed back the digital signal to the digital filter. | 10-31-2013 |