Patent application number | Description | Published |
20110246451 | STORAGE DEVICE HAVING FULL-TEXT SEARCH FUNCTION - According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request. | 10-06-2011 |
20120117354 | STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD - According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller. | 05-10-2012 |
20120139007 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si | 06-07-2012 |
20120218802 | CONTENT ADDRESSABLE MEMORY - One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET. | 08-30-2012 |
20120326224 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel. | 12-27-2012 |
20130042055 | MEMORY SYSTEM INCLUDING KEY-VALUE STORE - According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory. | 02-14-2013 |
20130042060 | MEMORY SYSTEM INCLUDING KEY-VALUE STORE - According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface. | 02-14-2013 |
20130069134 | MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES - In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region. | 03-21-2013 |
20130076392 | NONVOLATILE PROGRAMMABLE LOGIC SWITCH - A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively. | 03-28-2013 |
20130077397 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode. | 03-28-2013 |
20130080465 | STORAGE DEVICE HAVING FULL-TEXT SEARCH FUNCTION - According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request. | 03-28-2013 |
20130134499 | NONVOLATILE PROGRAMMABLE SWITCHES - A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases. | 05-30-2013 |
20130222011 | PROGRAMMABLE LOGIC SWITCH - One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. | 08-29-2013 |
20130241596 | PROGRAMMABLE LOGIC DEVICE - One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire. | 09-19-2013 |
20130248959 | PROGRAMMABLE LOGIC SWITCH - According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line. | 09-26-2013 |
20130258782 | CONFIGURATION MEMORY - According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node. | 10-03-2013 |
20130307054 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories. | 11-21-2013 |
20140035619 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CITCUIT - According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. | 02-06-2014 |
20140131811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a first transistor having a first source region and a first drain region arranged in a first protruded semiconductor region, a first channel region having a first corner portion in its upper portion in a section perpendicular to a first direction, the first corner portion having a first radius of curvature; a second transistor having a second source region and a second drain region arranged in a second protruded semiconductor region, and a second channel region having a second corner portion in its upper portion in a section that is perpendicular to a second direction, the second corner portion having a second radius of curvature greater than the first radius of curvature. | 05-15-2014 |
20150014748 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. | 01-15-2015 |
20150074341 | MEMORY SYSTEM INCLUDING KEY-VALUE STORE - According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface. | 03-12-2015 |