Korablev
Dmitri Korablev, Walnut Creek, CA US
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20120233689 | SYSTEM AND METHOD FOR EFFICIENTLY SECURING ENTERPRISE DATA RESOURCES - Some embodiments provide a system and method that secures access to data objects of an enterprise that includes multiple data objects and multiple user applications that access data attributes of the data objects. In some embodiments, secure access is provided via a secure resource that secures access to data attributes of at least two objects by defining access control permissions for the secure resource and applying the defined access control permissions to the data attributes of the secure resource. | 09-13-2012 |
20120324592 | SYSTEM AND METHOD FOR FLEXIBLE SECURITY ACCESS MANAGEMENT IN AN ENTERPRISE - Some embodiments provide a method and system for flexibly managing access to enterprise resources. To flexibly manage security, some embodiments secure the enterprise resources and provide a security access manager (SAM) to control access to the secured resources. The SAM controls access to the enterprise and the secure resources through one or more configurable management modules of the SAM. Each management module of the SAM is configurable to facilitate control over different security services of an enterprise security hierarchy (e.g., authentication, authorization, role mapping, etc.). Specifically, each management module is configurable to leverage security services that are provided by different security systems. In some embodiments, the management module is configured to interface with one or more adapters in order to establish the interfaces, logic, and protocols necessary to leverage the security functionality of such security systems. | 12-20-2012 |
Konstantin Korablev, Saratoga Springs, NY US
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20140131831 | INTEGRATED CIRUIT INCLUDING AN FIN-BASED DIODE AND METHODS OF ITS FABRICATION - A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin. | 05-15-2014 |
Konstantin G. Korablev, Sunnyvale, CA US
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20100102390 | Gated diode with increased voltage tolerance - In a gated diode ESD protection structure, the gate is biased to a voltage higher than ground and gate size is reduced while ensuring adequate spacing between p+ and n+ regions of the diode by blocking at least one of n-lightly doped region and p-lightly doped region. | 04-29-2010 |
20100102391 | Split-gate ESD diodes with elevated voltage tolerance - In a gated diode ESD protection structure, the gate is split into two parts to divide the total reverse voltage between two gate regions. | 04-29-2010 |
20120176707 | ESD clamp with auto biasing under high injection conditions - In an SCR ESD protection circuit, the n-type emitter of the SCR is controlled to receive electron current only during an ESD event, thereby defining PNP characteristics during normal operation and SCR characteristics during an ESD event. | 07-12-2012 |
Konstantin G. Korablev, Saratoga Springs, NY US
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20150270400 | SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS - Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device). | 09-24-2015 |