Patent application number | Description | Published |
20100085231 | DATA PROCESSING DEVICE COMPRISING ADC UNIT | 04-08-2010 |
20100153041 | ERROR PROCESSING IN TIME INTERLEAVED SIGNAL PROCESSING DEVICES - The present invention relates to a signal processing apparatus comprising a signal input and a signal output; a plurality of signal processing units, wherein each signal processing unit having the same structure and at least one spatial error, being connected to the signal input, and being adapted to subject an input signal from the signal input to predetermined signal processing; selection means configured to select and form a predetermined number of groups from the plurality of signal processing units in accordance with a predetermined criterion; and control means for controlling the groups of the signal processing units to be active in a time interleaved schema, wherein an active group provides a respective processed input signal as an output signal to the signal output; wherein the plurality of signal processing units comprises more signal processing units as required to realize a predetermined time interleaving factor. | 06-17-2010 |
20100302082 | DEVICE FOR RECEIVING A RF SIGNAL WITH LOOP-THROUGH OUTPUT AND METHOD FOR LOOPING A RF INPUT SIGNAL THROUGH A DEVICE FOR RECEIVING RF SIGNALS - A device for receiving a RF signal ( | 12-02-2010 |
20110012771 | FLASH ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter comprises a signal input ( | 01-20-2011 |
20110109811 | FAST SERVICE SCAN - A method of performing a service scan for available channels across a bandwidth of an input signal, the method comprising the steps of: acquiring a power spectrum of the input signal bandwidth; analysing the power spectrum to identify a list of candidate channels, each candidate channel being identified by at least a centre frequency; processing each of the candidate channels in a receiver unit to extract service information, if present, relating to the candidate channel; and storing the service information for the channel in a memory. | 05-12-2011 |
20110241912 | ADC - This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration. | 10-06-2011 |
20120274362 | TRACKING AND HOLD OPERATIONS FOR AN ANALOG-TO-DIGITAL CONVERTER - Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase. | 11-01-2012 |
20130033392 | SUCCESSIVE APPROXIMATION REGISTER ADC CIRCUITS AND METHODS - A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process. | 02-07-2013 |