Patent application number | Description | Published |
20090256848 | Filtering Method and Apparatus for Anti-Aliasing - Embodiments of a filtering method and apparatus for anti-aliasing as described herein take advantage of improved existing hardware by using as input the data stored in the multisampling anti-aliasing (MSAA) buffers after rendering. The standard hardware box-filter is then replaced with a more intelligent resolve implemented using shader programs. Embodiments find scene edges using existing samples generated by Graphics Processing Unit (GPU) hardware. Using samples from a footprint larger than a single pixel, a gradient is calculated matching the direction of an edge. A non-linear filter over contributing samples in the direction of the gradient gives the final result. | 10-15-2009 |
20090274366 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 11-05-2009 |
20100245374 | METHOD AND APPARATUS FOR ANGULAR INVARIANT TEXTURE LEVEL OF DETAIL GENERATION - A method and apparatus for angular invariant texture level of detail calculation is disclosed. The method includes a determination for a LOD that determines angular invariant LODs that result in efficient ASIC hardware implementation. | 09-30-2010 |
20110050710 | Internal, Processing-Unit Memory For General-Purpose Use - Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system. | 03-03-2011 |
20120002873 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 01-05-2012 |
20120320067 | REAL TIME ON-CHIP TEXTURE DECOMPRESSION USING SHADER PROCESSORS - A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU. | 12-20-2012 |
20130073755 | DEVICE PROTOCOL TRANSLATOR FOR CONNECTION OF EXTERNAL DEVICES TO A PROCESSING UNIT PACKAGE - A processing unit package includes a processing unit disposed on an interposer and a device protocol translator disposed on the interposer. Through-silicon vias (TSVs) may be used to provide connections from the device protocol translator through the interposer to an external device. The device protocol translator uses a controller to control a plurality of buffers that store information received from respective information buses coupled to the processing unit, such that the processing unit information is translated according to a protocol of the external device. | 03-21-2013 |
20130094775 | REGION-BASED IMAGE COMPRESSION - A method for compressing an image includes decomposing the image into one or more regions. A region of the image is selected to be evaluated. The selected region is transformed and quantized if the region does not meet a predetermined compression acceptability criteria. The predetermined compression acceptability criteria may include a specific bit rate, a specific image quality, or combinations thereof. If the region does not meet the predetermined compression acceptability criteria after the region has been transformed and quantized, then the transformation and quantization settings are adjusted and the region is transformed and quantized using the adjusted settings. The region is then encoded when the predetermined compression acceptability criteria has been reached. The encoding may include additional compression stages. | 04-18-2013 |
20130106902 | FILTERING METHOD AND APPARATUS FOR ANTI-ALIASING | 05-02-2013 |
20130141442 | METHOD AND APPARATUS FOR MULTI-CHIP PROCESSING - Various methods, computer-readable mediums and apparatus are disclosed. In one aspect, a method of generating a graphical image on a display device is provided that includes splitting geometry level processing of the image between plural processors coupled to an interposer. Primitives are created using each of the plural processors. Any primitives not needed to render the image are discarded. The image is rasterized using each of the plural processors. A portion of the image is rendered using one of the plural processors and any remaining portion of the image using one or more of the other plural processors. | 06-06-2013 |
20130315481 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 11-28-2013 |
20160105677 | HYBRID BLOCK BASED COMPRESSION - A method and apparatus is provided for block based compression of a texture using hardware supported compression formats. The method comprises dividing a texture into a plurality of blocks, for each block, determining a transform for use with the block to minimize an error metric, encoding at least one characteristic of the transform into a plurality of bits otherwise available to represent reference component values, and compressing the block. | 04-14-2016 |
Patent application number | Description | Published |
20100035382 | Methods of making compliant semiconductor chip packages - A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate. A bond ribbon can include a strip extending along the sloping surface of the compliant layer, the strip having a substantially constant thickness in a direction extending away from the sloping surface. | 02-11-2010 |
20110095441 | MICROELECTRONIC ASSEMBLIES HAVING COMPLIANT LAYERS - A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip. | 04-28-2011 |
20140042634 | METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES - A semiconductor chip package is fabricated including providing a compliant layer over a contact bearing face of a semiconductor chip, with a bottom surface of the compliant layer adjacent that chip face, a top surface facing away from the bottom surface, and at least one sloping surface extending between the top and bottom surfaces. Bond ribbons can be formed atop the compliant layer, each bond ribbon electrically coupling one of the contacts with an associated conductive terminal at the top surface of the compliant layer. A bond ribbon can include a strip extending along the sloping surface. The strip may have a substantially constant thickness in a direction away from the sloping surface. | 02-13-2014 |
20150194347 | METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES - A compliant layer is provided over a face of an undiced semiconductor wafer to form a portion of said compliant layer over each of a plurality of semiconductor chips integral with one another in the undiced wafer, each semiconductor chip having a plurality of contacts at its face. The compliant layer has a bottom surface adjacent the chip face, a top surface facing away from the bottom surface, and a sloping surface between the top and bottom surfaces. Bond ribbons of electrically conductive material are formed each extending from a contact of a respective semiconductor chip, along the sloping surface and the top surface of a portion of the compliant layer to a terminal supported by the top surface of the compliant layer. The packages are then separated from one another by dicing the wafer at semiconductor chip boundaries. | 07-09-2015 |
20150334825 | EMBEDDED TRACES - A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic core material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material. | 11-19-2015 |
20150334826 | EMBEDDED TRACES - A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material. | 11-19-2015 |
20150334836 | VIA IN A PRINTED CIRCUIT BOARD - A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole. | 11-19-2015 |