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| 20100055422 | Electroless Deposition of Platinum on Copper - Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices. | 03-04-2010 |
| 20100203731 | Formation of a Zinc Passivation Layer on Titanium or Titanium Alloys Used in Semiconductor Processing - Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl | 08-12-2010 |
| 20120091590 | Electroless Deposition of Platinum on Copper - Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices. | 04-19-2012 |
| 20120295436 | FORMATION OF A ZINC PASSIVATION LAYER ON TITANIUM OR TITANIUM ALLOYS USED IN SEMICONDUCTOR PROCESSING - Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl | 11-22-2012 |
| 20120325109 | Formation of A Zinc Passivation Layer on Titanium or Titanium Alloys Used in - Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl | 12-27-2012 |
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| 20090291275 | Methods For Improving Selectivity of Electroless Deposition Processes - Methods for improving selective deposition of a capping layer on a patterned substrate are presented, the method including: receiving the patterned substrate, the patterned substrate including a conductive region and a dielectric region; forming a molecular masking layer (MML) on the dielectric region; preparing an electroless (ELESS) plating bath, where the ELESS plating bath includes: a cobalt (Co) ion source: a complexing agent: a buffer: a tungsten (W) ion source: and a reducing agent; and reacting the patterned substrate with the ELESS plating bath for an ELESS period at an ELESS temperature and an ELESS pH so that the capping layer is selectively formed on the conductive region. In some embodiments, methods further include a pH adjuster for adjusting the ELESS pH to a range of approximately 9.0 pH to 9.2 pH. In some embodiments, the pH adjuster is tetramethylammonium hydroxide (TMAH). In some embodiments, the MML is hydrophilic. | 11-26-2009 |
| 20110207320 | Noble Metal Activation Layer - Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials | 08-25-2011 |
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| 20090043955 | Configurable high-speed memory interface subsystem - A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal. | 02-12-2009 |
| 20090091349 | High speed multiple memory interface I/O cell - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode. | 04-09-2009 |
| 20090091987 | Multiple memory standard physical layer macro function - A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers. | 04-09-2009 |
| 20090187873 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist. | 07-23-2009 |
| 20100157700 | APPARATUS AND SYSTEMS FOR VT INVARIANT DDR3 SDRAM WRITE LEVELING - Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period. | 06-24-2010 |
| 20110084725 | HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode. | 04-14-2011 |
| 20110258587 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist. | 10-20-2011 |
| 20120194248 | NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA STROBE - A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects. | 08-02-2012 |
| 20120195141 | GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING MEMORY CONTROLLER AND SOURCE SYNCHRONOUS MEMORY - A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock. | 08-02-2012 |
| 20120278783 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path. | 11-01-2012 |
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| 20110208570 | APPARATUS, SYSTEM, AND METHOD FOR INDIVIDUALIZED AND DYNAMIC ADVERTISEMENT IN CLOUD COMPUTING AND WEB APPLICATION - An apparatus, system, and method are disclosed for individualized and dynamic advertisements delivery and display in cloud computing and ordinary Internet systems. The client updates the advertisement server periodically the user web browsing history and local media, advertisements play back log. The client updates the advertisement server the user geographical location. The advertisement server analyzes the user interest and geographical information from client, combining with the server information of client neighborhood events, client neighboring friends, traffic, weather condition. The advertisement server selects the advertisements, tags the selected advertisements, then pushes to the client local storage. Client takes the retrieved web content and selects the best fit advertisements from local storage with according to the time, date, as well as the information of browsing history, geographical information, neighborhood events, client neighboring friends, traffic, weather. The client constructs new web pages with the individualized advertisements. The individualized advertisements can be added to the original web pages, or replace original advertisements. | 08-25-2011 |
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| 20100226124 | Lighting fixture with adjustable light pattern and foldable house structure - A lighting fixture includes a reflector reflecting light from a fluorescent lamp to a desired direction, and one or more lamp connectors connecting the reflector to rotatably and detachably coupling with the fluorescent lamp, wherein the reflector is adapted to selectively rotate with respect to an axis of the fluorescent lamp for reflecting light from the fluorescent lamp so as to change a light pattern of the fluorescent lamp towards an opening of the foldable housing. The foldable housing includes two side frames and a retention frame extended between the two side frames to retain a distance therebetween, wherein the side frames are pivotally coupled with the retention frame to fold between an unfolded position to retain the fluorescent lamp in longitudinal position and a folded position to form a compact size for storage and transportation. | 09-09-2010 |
| 20120063140 | Lighting fixture with adjustable light pattern and foldable house structure - A lighting fixture includes a reflector reflecting light from a fluorescent lamp to a desired direction, and one or more lamp connectors connecting the reflector to rotatably and detachably coupling with the fluorescent lamp, wherein the reflector is adapted to selectively rotate with respect to an axis of the fluorescent lamp for reflecting light from the fluorescent lamp so as to change a light pattern of the fluorescent lamp towards an opening of the foldable housing. The foldable housing includes two side frames and a retention frame extended between the two side frames to retain a distance therebetween, wherein the side frames are pivotally coupled with the retention frame to fold between an unfolded position to retain the fluorescent lamp in longitudinal position and a folded position to form a compact size for storage and transportation. | 03-15-2012 |
| 20120091880 | High performance fluorescent lamp - A high performance fluorescent lamp includes an air-tight glass envelop having sealed ends and a light cavity filled with inert gas and coated with a phosphor powder at an inner wall of the glass envelop. Two filaments are sealed at the sealed ends of the glass envelop respectively. A channel is formed at one of the sealed ends of the glass envelop at a location communicating with the light cavity of the glass envelop. An amalgam is retained within the channel at a position forming a preset distance between the respective filament and the amalgam. Therefore, the fluorescent lamp can be operated under different ambient temperature or different wattage of the fluorescent lamp with the similar type of amalgam by controlling a distance between the amalgam and the respective filament. | 04-19-2012 |
| 20120281397 | Lighting Fixture with Adjustable Light Pattern and Extendable House Structure - A lighting fixture includes a reflector reflecting light from a fluorescent lamp to a desired direction, and one or more lamp connectors connecting the reflector to rotatably and detachably coupling with the fluorescent lamp, wherein the reflector is adapted to selectively rotate with respect to an axis of the fluorescent lamp for reflecting light from the fluorescent lamp so as to change a light pattern of the fluorescent lamp towards an opening of the foldable housing. The foldable housing includes two side frames and a retention frame extended between the two side frames to retain a distance therebetween, wherein the side frames are pivotally coupled with the retention frame to fold between an unfolded position to retain the fluorescent lamp in longitudinal position and a folded position to form a compact size for storage and transportation. | 11-08-2012 |
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| 20110038562 | Universal Front End for Masks, Selections, and Paths - A method, system, and computer-readable storage medium are disclosed for editing a digital image with automatic conversion of region modalities. Input comprising an instruction to perform an operation on a first portion of the digital image may be received. The first portion of the digital image may comprise data defined by a first region modality. The operation may be applicable to data defined by a second region modality. In response to receiving the input, the first portion of the digital image may be automatically converted from the first region modality to the second region modality. The operation may be automatically performed on the converted first portion of the digital image (i.e., as defined by the second region modality). | 02-17-2011 |
| 20130034299 | Robust Patch Regression based on In-Place Self-similarity for Image Upscaling - Methods and systems for image upscaling are disclosed. In one embodiment, a low frequency band image intermediate is obtained from an input image. The input image is upsampled by a scale factor to obtain an upsampled image intermediate. A result image is estimated based at least in part on the upsampled image intermediate, the low frequency band image intermediate, and the input image, wherein the input image is of a smaller scale than the result image. | 02-07-2013 |
| 20130034311 | Denoising and Artifact Removal in Image Upscaling - Methods and systems for denoising and artifact removal in image upscaling are disclosed. In one embodiment, a low frequency band image intermediate is obtained from an input image. An upsampled image intermediate is obtained from the input image by upsampling. A result image is estimated, based at least in part on the upsampled image intermediate, the low frequency band image intermediate, and the input image. The input image is of a smaller scale than the result image. The estimating the result image further includes eliminating from the result image noise that is present in the input image. | 02-07-2013 |
| 20130034313 | Regression-Based Learning Model for Image Upscaling - Methods and systems for a regression-based learning model in image upscaling are disclosed. In one embodiment, a set of image patch pairs for each of a set of images is generated. Each of the image patch pairs contains a natural image and a corresponding downscaled lower-resolution image. A regression model based at least in part on the set of image patch pairs is defined. The regression model represents a gradient of a function of the downscaled lower-resolution image. An image is upscaled based at least in part on the regression model. | 02-07-2013 |
| 20130058587 | Motion Deblurring for Text Images - Various embodiments of methods and apparatus for motion deblurring in text images are disclosed. In one embodiment, a threshold-based text prediction for a blurred image is generated. A point spread function for the blurred image is estimated. A result of the threshold-based text prediction function is deconvolved based on the point spread function. The generating, estimating, and deconvolving are iterated at a plurality of scales, and a final deconvolution of a result of the iteratively deconvolving is executed. | 03-07-2013 |
| 20130058588 | Motion Deblurring Using Image Upsampling - Various embodiments of methods and apparatus for motion deblurring are disclosed. In one embodiment, an estimate of a latent image of a blurred image at a current scale from an estimate of a latent image at a previous coarse scale is generated using an upsampling super-resolution function, and a blur kernel is estimated based on the estimate of the latent image and the blurred image; and are repeated from a course to fine scale. A final image estimate is generated. The generating the final image estimate includes performing a deconvolution of the latent image using the blur kernel and the blurred image. | 03-07-2013 |
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| 20080255023 | Low Residue Cleaning Solution - The present invention relates to cleaning compositions containing C8-C10 alkylpolyglucosides which have low filming and streaking when combined with C2-C4 alcohols. The cleaning compositions can optionally comprise dyes, builders, fatty acids, fragrances, colorants, glycerol, anti-foaming agents, and preservatives. | 10-16-2008 |
| 20090118154 | Acidic Cleaning Compositions - A cleaning composition with a limited number of natural ingredients contains alkyl polyglucoside, a 2-hydroxylcarboxylic acid, and a fragrance containing lemon oil or d-limonene. The cleaning composition optionally has a small amount of dye, colorant, and preservative. The cleaning composition can be used to clean hard surfaces and cleans as well or better than commercial compositions containing synthetically derived cleaning agents. | 05-07-2009 |
| 20100330139 | Substrate With Low Residue Cleaning Composition - The present invention relates to substrate loaded with a cleaning composition containing C8-C10 alkylpolyglucosides which have low filming and streaking when combined with C2-C4 alcohols. The cleaning composition may also comprises a C2 to C4 alcohol, a water-soluble organic acid and a glycerol. The cleaning composition may optionally comprise dyes, builders, fatty acids, fragrances, colorants, glycerol, anti-foaming agents, and preservatives. The nonwoven substrate material comprises unmodified and modified natural fibers. The nonwoven substrate material is at least 90% biodegradable under compost conditions. The substrate loaded with the cleaning composition is also at least 90% biodegradable under compost conditions. | 12-30-2010 |
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| 20110229734 | Immersion platinum plating solution - A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces. | 09-22-2011 |
| 20120012897 | Vertically Fabricated BEOL Non-Volatile Two-Terminal Cross-Trench Memory Array with Two-Terminal Memory Elements and Method of Fabricating the Same - A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required. | 01-19-2012 |
| 20120315503 | IMMERSION PLATINUM PLATING SOLUTION - A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces. | 12-13-2012 |
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| 20090325260 | CIS REACTIVE OXYGEN QUENCHERS INTEGRATED INTO LINKERS - The present invention provides methods and compositions for performing illuminated reactions, particularly sequencing reactions, while mitigating and/or preventing photodamage to reactants that can result from prolonged illumination. In particular, the invention provides methods and compositions for incorporating photoprotective agents into conjugates comprising reporter molecules and nucleoside polyphosphates. | 12-31-2009 |
| 20100136592 | Photo-Induced Damage Mitigating Agents and Preparation and Methods of Use Thereof - Compositions, devices, systems and methods for reducing and/or preventing photo-induced damage of one or more reactants in an illuminated analytical reaction by addition of one or more photo-induced damage mitigating agents to the reaction mixture and allowing the reaction to proceed for a period that is less than a photo-induced damage threshold period. | 06-03-2010 |
| 20100255488 | FRET-LABELED COMPOUNDS AND USES THEREFOR - FRET-labeled compounds are provided for use in analytical reactions. In certain embodiments, FRET-labeled nucleotide analogs are used in place of naturally occurring nucleoside triphosphates or other analogs in analytical reactions comprising nucleic acids, for example, template-directed nucleic acid synthesis, DNA sequencing, RNA sequencing, single-base identification, hybridization, binding assays, and other analytical reactions. | 10-07-2010 |
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| 20100321102 | Leakage Reduction in Electronic Circuits - In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode. | 12-23-2010 |
| 20110193589 | On-Chip Sensor For Measuring Dynamic Power Supply Noise Of The Semiconductor Chip - An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured. | 08-11-2011 |
| 20120109356 | Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection - In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit. | 05-03-2012 |
| 20120112809 | METHOD AND DIGITAL CIRCUIT FOR GENERATING A WAVEFORM FROM STORED DIGITAL VALUES - In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path. | 05-10-2012 |
| 20120177159 | Full Digital Bang Bang Frequency Detector with No Data Pattern Dependency - A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data. | 07-12-2012 |
| 20120218005 | Semiconductor Device Having On-Chip Voltage Regulator - A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage. | 08-30-2012 |
| 20130030767 | HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK - System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock. | 01-31-2013 |
| 20130033287 | Balanced Single-Ended Impedance Control - A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively. | 02-07-2013 |
| 20130033329 | System and Method of Controlling Gain of an Oscillator - A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process. | 02-07-2013 |
