| Patent application number | Description | Published |
|---|
| 20080254588 | METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM - A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %. | 10-16-2008 |
| 20100001369 | DEVICE LAYOUT FOR GATE LAST PROCESS - A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region. | 01-07-2010 |
| 20100052058 | DOWNSIZE POLYSILICON HEIGHT FOR POLYSILICON RESISTOR INTEGRATION OF REPLACEMENT GATE PROCESS - A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure. | 03-04-2010 |
| 20100052065 | NEW METHOD FOR MECHANICAL STRESS ENHANCEMENT IN SEMICONDUCTOR DEVICES - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region. | 03-04-2010 |
| 20100065915 | CHEMICAL MECHANICAL POLISHING (CMP) METHOD FOR GATE LAST PROCESS - A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure. | 03-18-2010 |
| 20100270627 | METHOD FOR PROTECTING A GATE STRUCTURE DURING CONTACT FORMATION - A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions. | 10-28-2010 |
| 20110195549 | GATE STACK FOR HIGH-K/METAL GATE LAST PROCESS - A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device. | 08-11-2011 |
| 20110233683 | CHEMICAL MECHANICAL POLISHING (CMP) METHOD FOR GATE LAST PROCESS - A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure. | 09-29-2011 |
