Kokolakis

Ioannis Kokolakis, Holargos GR

Patent application number	Description	Published
20100040184	METHOD AND SYSTEM FOR COEXISTENCE IN A MULTIBAND, MULTISTANDARD COMMUNICATION SYSTEM UTILIZING A PLURALITY OF PHASE LOCKED LOOPS - Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.	02-18-2010

Patent application number	Description	Published
20090128992	MOS CAPACITOR STRUCTURE AND LINEARIZATION METHOD FOR REDUCED VARIATION OF THE CAPACITANCE - A highly linearized capacitor structure is formed by a first capacitor, that is coupled between a first terminal and a common node, combine with a second capacitor, that is coupled between a second terminal and the common node. When a bias voltage is applied, the capacitance values of the first and second capacitors combine and a capacitance variation of the first capacitor is compensated by a capacitance variation of the second capacitor to reduce and linearize overall capacitance variation in the combined capacitor structure.	05-21-2009

Patent application number	Description	Published
20110018604	Configurable Clock Signal Generator - A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.	01-27-2011