| Patent application number | Description | Published |
| 20090012128 | MICROBICIDAL AGENT AND MICROBICIDAL COMPOSITION - A microbicidal agent comprising as an effective ingredient at least one selected from the group consisting of p-hydroxybenzaldehyde, 5,7,4′-trihydroxy-3′,5′-dimethoxyflavone, 3-hydroxypyridine and vanillin, and a microbicidal composition comprising the microbicidal agent. | 01-08-2009 |
| 20100121083 | ANTI-VIRAL AGENT - Provided is an antiviral agent with high antiviral activities and low side effects (cytotoxicity). Specifically provided is an antiviral agent comprising as an effective component at least one member selected from the group consisting of 5,7,4′-trihydroxy-3′,5′-dimethoxyflavone, 3-hydroxypyridine, p-hydroxybenzaldehyde and vanillin. | 05-13-2010 |
| 20100190846 | MICROBICIDAL AGENT AND MICROBICIDAL COMPOSITION - A method for suppressing the growth of microorganism comprises the steps of providing a microbicidal agent comprising 5,7,4′-trihydroxy-3′,5′-dimethoxyflavone, and contacting the agent with the microorganism, wherein said microorganism is selected from the group consisting of | 07-29-2010 |
| Patent application number | Description | Published |
| 20080211029 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced. | 09-04-2008 |
| 20080220580 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device. | 09-11-2008 |
| 20090065888 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a main surface of a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region in circular form, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other. | 03-12-2009 |
| 20090206411 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P | 08-20-2009 |
| 20100244137 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced. | 09-30-2010 |
| 20110180877 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P | 07-28-2011 |
| Patent application number | Description | Published |
| 20080300349 | Flame-Retardant Polyester and Process for Producing the Same - To easily obtain a polyester having excellent mechanical properties, a satisfactory hue, and a high degree of flame retardancy. [MEANS FOR SOLVING PROBLEMS] The flame-retardant polyester is a polyester comprising ethylene terephthalate units as the main structural units and a phosphorus compound copolymerized or incorporated therein or is a resin composition comprising polyesters including that polyester. The flame-retardant polyester is characterized in that a polycarboxylic acid and/or polyol having three or more functional groups capable of forming an ester bond is contained in the polyester in a total amount of 0.05-2.00 mol (per 200 mol of the sum of the dicarboxylic acid ingredient and the diol ingredient), that a specific phosphorus compound having a functional group capable of forming an ester bond is contained in the polyester in an amount of 5,000-50,000 ppm of the polyester in terms of phosphorus amount, and that the polyester pellet obtained has a b value of −5 to 20, an L value of 35 or larger, and a melt viscosity at 280° C. of 1,000-20,000 dPa·s. | 12-04-2008 |
| 20090203871 | METHOD FOR PRODUCING THERMOPLASTIC POLYESTER ELASTOMER, THERMOPLASTIC POLYESTER ELASTOMER COMPOSITION, AND THERMOPLASTIC POLYESTER ELASTOMER - The present invention provides a thermoplastic polyester elastomer excellent in heat resistance, heat-aging resistance, water resistance, light resistance, low-temperature property and the like, and further excellent in block order-retaining ability, the thermoplastic polyester elastomer comprising a hard segment which comprises polyester constituted with aromatic dicarboxylic acid and aliphatic or alicyclic diol and a soft segment which comprises mainly aliphatic polycarbonate, wherein the hard segment and the soft segment being connected, and wherein when melting points of the thermoplastic polyester elastomer are obtained by measuring on a differential scanning calorimeter in three cycles in which a temperature is raised from room temperature to 300° C. at a heating rate of 20° C./min., maintained at 300° C. for 3 minutes and lowered to room temperature at a cooling rate of 100° C./min., a melting point difference (Tm | 08-13-2009 |